diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 2cee4183a..f8b0d983f 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -109,8 +109,6 @@ module controller(
   logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
   logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
   logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
-  logic        bclrD, bextD;                   // Indicates if is one of these instructions
-  logic        andnD, ornD, xnorD;             // Indicates if is one of these instructions
   logic        maxE, maxuE, minE, minuE;       // Indicates if is one of these instructions in Execute Stage
   logic        BranchTakenE;                   // Branch is taken
   logic        eqE, ltE;                       // Comparator outputs
@@ -222,27 +220,13 @@ module controller(
     assign sltD = (Funct3D == 3'b010);
   end
 
-  if (`ZBS_SUPPORTED) begin
-    assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]);
-    assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]);
-  end else begin 
-    assign bclrD = 1'b0;
-    assign bextD = 1'b0;
-  end
-
   if (`ZBB_SUPPORTED) begin
-    assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]);
-    assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]);
-    assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]);
     // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator.
     assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]);
     assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]);
     assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]);
     assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]);
   end else begin
-    assign andnD = 0;
-    assign ornD = 0;
-    assign xnorD = 0;
     assign maxE = 0;
     assign maxuE = 0;
     assign minE = 0;