Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

pipelined/src/cache/cache.sv

@@ -171,7 +171,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   assign SetDirtyWay = SetDirty ? SelectedWay : '0;
   assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
   
-
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Cache FSM
   /////////////////////////////////////////////////////////////////////////////////////////////

pipelined/src/cache/cachereplacementpolicy.sv

@@ -46,6 +46,7 @@ module cachereplacementpolicy
   logic [SETLEN-1:0]                   RAdrD;
   logic                                LRUWriteEnD;
 
+  // *** high priority to clean up
   initial begin
       assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
   end

pipelined/src/cache/subcachelineread.sv

@@ -54,12 +54,12 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
     assign ReadDataLinePad = {Pad, ReadDataLine};    
   end else assign ReadDataLinePad = ReadDataLine;
 
-
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
 	  assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
   end
   // variable input mux
+  // *** maybe remove REPLAY config later after deciding which way is best
   assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]];
   if(!`REPLAY) begin
     flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);

pipelined/src/ieu/controller.sv

@@ -51,12 +51,12 @@ module controller(
   output logic [2:0] Funct3E,
   output logic       MDUE, W64E,
   output logic       JumpE,	
+  output logic       SCE,
+  output logic [1:0] AtomicE,
   // Memory stage control signals
   input  logic       StallM, FlushM,
   output logic [1:0] MemRWM,
   output logic       CSRReadM, CSRWriteM, PrivilegedM,
-  output logic       SCE,
-  output logic [1:0] AtomicE,
   output logic [1:0] AtomicM,
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit

pipelined/src/lsu/atomic.sv

@@ -52,7 +52,7 @@ module atomic (
   amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
                 .result(AMOResult));
   mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
-    assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
+  assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; // *** is DTLBMiss needed; might be par tof ignorerequest
   lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
     .SquashSCW, .LSURWM);
 

pipelined/src/lsu/busdp.sv

@@ -65,9 +65,11 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   output logic                BusStall,
   output logic                BusCommittedM);
   
-
   localparam integer   WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
   logic [`PA_BITS-1:0]        LocalLSUBusAdr;
+
+  // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem
+  // *** better name than DCacheBusWriteData
   genvar                      index;
   for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
     logic [WORDSPERLINE-1:0] CaptureWord;
@@ -80,9 +82,8 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), 
     .s(SelUncachedAdr), .y(LSUBusSize));
 
-  busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) 
+  busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
-  busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
+    .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
 		.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
 		.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
-
 endmodule

pipelined/src/lsu/interlockfsm.sv

@@ -96,6 +96,9 @@ module interlockfsm(
 	endcase
   end // always_comb
 	  
+  // *** change test to not propagate xs  so that we can return to excluded code
+  // might have changed name to WALLY-MMU-SV39?
+
   // signal to CPU it needs to wait on HPTW.
   /* -----\/----- EXCLUDED -----\/-----
    // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction.  InterlockStall becomes x and it propagates
@@ -119,12 +122,10 @@ module interlockfsm(
 	endcase
   end
   
-  
   assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
   assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
 				   (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
   assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM));
   assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) |
 							  ((InterlockCurrState == STATE_T0_REPLAY) & (TrapM));
-
 endmodule

pipelined/src/lsu/lsu.sv

@@ -106,6 +106,8 @@ module lsu (
   logic                     DataDAPageFaultM;
   logic [`XLEN-1:0]         LSUWriteDataM;
     
+  // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, 
+
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   assign IEUAdrExtM = {2'b00, IEUAdrM}; 
   assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
@@ -124,7 +126,6 @@ module lsu (
       .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
       .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
       .IgnoreRequestTLB, .IgnoreRequestTrapM);
-
   end else begin
     assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
     assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM; 
@@ -186,7 +187,10 @@ module lsu (
   logic                SelUncachedAdr;
   assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
   
+  // *** change to allow TIM and BUS.  seaparate parameter for having bus (but have to have bus if have cache - check in testbench)
   if (`DMEM == `MEM_TIM) begin : dtim
+    // *** directly instantiate RAM or ROM here.  Instantiate SRAM1P1RW.  
+    // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
     dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
               .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
               .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM,
@@ -227,7 +231,7 @@ module lsu (
 
     if(CACHE_ENABLED) begin : dcache
       logic [1:0] RW, Atomic;
-      assign RW = CacheableM ? LSURWM : 2'b00;        // AND gate
+      assign RW = CacheableM ? LSURWM : 2'b00;        // AND gate  // *** move and gates into cache
       assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache(
@@ -240,7 +244,7 @@ module lsu (
         .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), 
         .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
 
-      subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
+      subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(  // *** merge into cache
         .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
         .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM));
 
@@ -250,7 +254,7 @@ module lsu (
     end
   end
 
-  if(`DMEM != `MEM_BUS) begin
+  if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS.  Only produces byte write enable
     logic [`XLEN-1:0] ReadDataWordMaskedM;
     assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
     subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),

pipelined/src/lsu/lsuvirtmen.sv

@@ -86,12 +86,13 @@ module lsuvirtmem(
     .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
     .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
     .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
-  hptw hptw( // *** remove logic from (), mention this in style guide CH3
+  hptw hptw( 
     .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
     .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
     .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM,
-    .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),
+    .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),  // *** should it be HPTWReadDataM
     .DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize);
+  // *** possible future optimization of simplifying page table entry with precomputed misalignment (Ross) low priority
 
   // multiplex the outputs to LSU
   mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);