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https://github.com/openhwgroup/cvw
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Fixed FSM to continue transmitting after delay.
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parent
35c9fe7648
commit
419030bc33
@ -148,7 +148,8 @@ module spi_controller (
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// assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
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assign LastBit = BitNum == 3'd7;
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assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame;
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//assign EndOfFrame = SCLKenable & LastBit & Transmitting;
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assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrameDelay;
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assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay;
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always_ff @(posedge PCLK) begin
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@ -183,13 +184,13 @@ module spi_controller (
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if ((CurrState == INTERCS) & SCK & SCLKenable) begin
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INTERCSCounter <= INTERCSCounter + 8'd1;
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end else begin
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end else if (SCLKenable) begin
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INTERCSCounter <= 8'd0;
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end
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if ((CurrState == INTERXFR) & SCK & SCLKenable) begin
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INTERXFRCounter <= INTERXFRCounter + 8'd1;
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end else begin
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end else if (SCLKenable) begin
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INTERXFRCounter <= 8'd0;
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end
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@ -239,7 +240,7 @@ module spi_controller (
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end else begin
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ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
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PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset;
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SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting;
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SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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end
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end
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@ -284,12 +285,13 @@ module spi_controller (
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end
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SCKCS: begin // SCKCS case --------------------------------------
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if (EndOfSCKCS)
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if (EndTransmission)
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if (txFIFOReadEmpty) begin
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if (CSMode == AUTOMODE) NextState = INACTIVE;
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else if (CSMode == HOLDMODE) NextState = HOLD;
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else if (ContinueTransmit)
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end else if (~txFIFOReadEmpty) begin
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if (HasINTERCS) NextState = INTERCS;
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else NextState = TRANSMIT;
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end
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end
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HOLD: begin // HOLD mode case -----------------------------------
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if (CSMode == AUTOMODE) begin
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