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Fixed FSM to continue transmitting after delay.

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This commit is contained in:
Jacob Pease 2024-10-31 10:41:38 -05:00
parent 35c9fe7648
commit 419030bc33
1 changed files with 8 additions and 6 deletions
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14
src/uncore/spi_controller.sv
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@ -148,7 +148,8 @@ module spi_controller (
// assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv; // assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
assign LastBit = BitNum == 3'd7; assign LastBit = BitNum == 3'd7;
assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame; //assign EndOfFrame = SCLKenable & LastBit & Transmitting;
assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrameDelay;
assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay; assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay;
always_ff @(posedge PCLK) begin always_ff @(posedge PCLK) begin
@ -183,13 +184,13 @@ module spi_controller (
if ((CurrState == INTERCS) & SCK & SCLKenable) begin if ((CurrState == INTERCS) & SCK & SCLKenable) begin
INTERCSCounter <= INTERCSCounter + 8'd1; INTERCSCounter <= INTERCSCounter + 8'd1;
end else begin end else if (SCLKenable) begin
INTERCSCounter <= 8'd0; INTERCSCounter <= 8'd0;
end end
if ((CurrState == INTERXFR) & SCK & SCLKenable) begin if ((CurrState == INTERXFR) & SCK & SCLKenable) begin
INTERXFRCounter <= INTERXFRCounter + 8'd1; INTERXFRCounter <= INTERXFRCounter + 8'd1;
end else begin end else if (SCLKenable) begin
INTERXFRCounter <= 8'd0; INTERXFRCounter <= 8'd0;
end end
@ -239,7 +240,7 @@ module spi_controller (
end else begin end else begin
ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset; ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset; PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset;
SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting; SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting & ~DelayIsNext;
EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting; EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
end end
end end
@ -284,12 +285,13 @@ module spi_controller (
end end
SCKCS: begin // SCKCS case -------------------------------------- SCKCS: begin // SCKCS case --------------------------------------
if (EndOfSCKCS) if (EndOfSCKCS)
if (EndTransmission) if (txFIFOReadEmpty) begin
if (CSMode == AUTOMODE) NextState = INACTIVE; if (CSMode == AUTOMODE) NextState = INACTIVE;
else if (CSMode == HOLDMODE) NextState = HOLD; else if (CSMode == HOLDMODE) NextState = HOLD;
else if (ContinueTransmit) end else if (~txFIFOReadEmpty) begin
if (HasINTERCS) NextState = INTERCS; if (HasINTERCS) NextState = INTERCS;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end
end end
HOLD: begin // HOLD mode case ----------------------------------- HOLD: begin // HOLD mode case -----------------------------------
if (CSMode == AUTOMODE) begin if (CSMode == AUTOMODE) begin