From 411997010b3e1c89a8e23d8499ccdcb0b4f2e3bc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Feb 2022 11:40:10 -0600 Subject: [PATCH] Replacement policy cleanup. --- pipelined/src/cache/cache.sv | 15 ++++------ pipelined/src/cache/cachereplacementpolicy.sv | 28 +++++++++---------- pipelined/src/cache/cacheway.sv | 8 +++--- pipelined/src/lsu/lsu.sv | 14 ++++------ 4 files changed, 28 insertions(+), 37 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 4f1788a33..a4f73e8f2 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -114,18 +114,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, - .WriteWordWayEn, - .WriteLineWayEn, - .CacheWriteData, - .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, - .SelEvict, .VictimWay, .FlushWay, - .SelFlush, - .ReadDataLineWay, .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay), - .InvalidateAll(InvalidateCacheM)); + .clk, .reset, .RAdr, .PAdr, .WriteWordWayEn, .WriteLineWayEn, .CacheWriteData, + .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, + .FlushWay, .SelFlush, .ReadDataLineWay, .WayHit, .VictimDirtyWay, .VictimTagWay, + .InvalidateAll(InvalidateCacheM)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .WayHit(WayHitFinal), .VictimWay, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .RAdr, .LRUWriteEn); + .clk, .reset, .WayHit(WayHitFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | WayHit; assign VictimDirty = | VictimDirtyWay; diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index c9bad7af9..66b2387c7 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -30,21 +30,19 @@ `include "wally-config.vh" module cachereplacementpolicy - #(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128) - (input logic clk, reset, - input logic [NUMWAYS-1:0] WayHit, - output logic [NUMWAYS-1:0] VictimWay, - input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdr, - input logic [INDEXLEN-1:0] RAdr, - input logic LRUWriteEn - ); + #(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( + input logic clk, reset, + input logic [NUMWAYS-1:0] WayHit, + output logic [NUMWAYS-1:0] VictimWay, + input logic [`PA_BITS-1:0] PAdr, + input logic [INDEXLEN-1:0] RAdr, + input logic LRUWriteEn); - logic [NUMWAYS-2:0] LRUEn, LRUMask; - logic [$clog2(NUMWAYS)-1:0] EncVicWay; - logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; - logic [NUMWAYS-2:0] LineReplacementBits; - logic [NUMWAYS-2:0] NewReplacement; - logic [NUMWAYS-2:0] NewReplacementD; + logic [NUMWAYS-2:0] LRUEn, LRUMask; + logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; + logic [NUMWAYS-2:0] LineReplacementBits; + logic [NUMWAYS-2:0] NewReplacement; + logic [NUMWAYS-2:0] NewReplacementD; logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdrD; logic [INDEXLEN-1:0] RAdrD; @@ -56,7 +54,7 @@ module cachereplacementpolicy // Pipeline Delay Registers flopr #(INDEXLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); - flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr, PAdrD); + flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN], PAdrD); flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index b4e8ad501..a5bb52812 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -52,8 +52,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, output logic [LINELEN-1:0] ReadDataLineWay, output logic WayHit, - output logic VictimDirty, - output logic [TAGLEN-1:0] VictimTag); + output logic VictimDirtyWay, + output logic [TAGLEN-1:0] VictimTagWay); localparam WORDSPERLINE = LINELEN/`XLEN; localparam LOGWPL = $clog2(WORDSPERLINE); @@ -92,8 +92,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // AND portion of distributed tag multiplexer assign SelTag = SelFlush ? FlushWay : VictimWay; - assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux - assign VictimDirty = SelTag & Dirty & Valid; + assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux + assign VictimDirtyWay = SelTag & Dirty & Valid; ///////////////////////////////////////////////////////////////////////////////////////////// // Data Array diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5ca1a7969..1151cd903 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -127,14 +127,11 @@ module lsu ( assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; end - // **** look into this confusing signal. - // This signal is confusing. CommittedM tells the CPU's trap unit the current instruction + // CommittedM tells the CPU's privilege unit the current instruction // in the memory stage is a memory operaton and that memory operation is either completed - // or is partially executed. This signal is only low for the first cycle of a memory - // operation. - // **** I think there is also a bug here. Data cache misses and TLB misses both - // set this bit in the first cycle. It is not strickly wrong, but it may be better - // to flush the memory operation at that time. + // or is partially executed. Partially completed memory operations need to prevent an interrupts. + // There is not a clean way to restore back to a partial executed instruction. CommiteedM will + // delay the interrupt until the LSU is in a clean state. assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; // MMU and Misalignment fault logic required if privileged unit exists @@ -238,7 +235,8 @@ module lsu ( .Funct3M(LSUFunct3M), .ReadDataM); // this might only get instantiated if there is a dcache or dtim. - // There is a copy in the ebu. *** is it needed there, or can data come in from ebu, get muxed here and sent back out + // There is a copy in the ebu. *** is it needed there, or can data come in from ebu, get + // muxed here and sent back out. // Explore changing feedback path from output of AMOALU to subword write *** subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),