mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into Z_enable
This commit is contained in:
commit
4107ec5b8e
@ -276,7 +276,7 @@ cd "$RISCV"
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# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
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# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
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if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
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if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
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cd "$RISCV"/riscv-gnu-toolchain
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cd "$RISCV"/riscv-gnu-toolchain
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git reset --hard && git clean -f && git checkout master && git pull
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git reset --hard && git clean -f && git checkout master && git pull && git submodule update
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./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
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./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
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make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
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make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
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if [ "$clean" ]; then
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if [ "$clean" ]; then
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@ -60,7 +60,7 @@ install: check_write_permissions check_environment
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dumptvs: check_write_permissions check_environment
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dumptvs: check_write_permissions check_environment
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$(SUDO) mkdir -p $(RISCV)/linux-testvectors
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$(SUDO) mkdir -p $(RISCV)/linux-testvectors
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cd testvector-generation; ./genInitMem.sh
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./genInitMem.sh
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@echo "Testvectors successfully generated."
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@echo "Testvectors successfully generated."
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generate: $(DTB) $(IMAGES)
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generate: $(DTB) $(IMAGES)
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@ -1,12 +0,0 @@
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00001000: 00000297 auipc t0, 0 # t0 = 0x00001000
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00001004: 02828613 addi a2, t0,0x28 # a2 = 0x00001028
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00001008: f1402573 csrr a0, mhartid # a0 = mhartid
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0000100c: 0202b583 ld a1, 32(t0) # a1 = 87000000 - device tree address
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00001010: 0182b283 ld t0, 24(t0) # t0 = 80000000 - start of firmware
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00001014: 00028067 jr t0 # jump to firmware
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00001018: 0000000080000000 # firmware start address
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00001020: 000000008fe00000 # flattened device tree load address
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00001028: 000000004942534f # a2 points to this 8 dword data structure
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00001030: 0000000000000002
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00001038: 0000000080200000
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00001040: 0000000000000001
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@ -46,9 +46,12 @@ echo "Launching QEMU in replay mode!"
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-ex "q"
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-ex "q"
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echo "Changing Endianness"
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echo "Changing Endianness"
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make fixBinMem
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# Extend files to 8 byte multiple
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./fixBinMem "$rawRamFile" "$ramFile"
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truncate -s %8 "$rawRamFile"
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./fixBinMem "$rawBootmemFile" "$bootmemFile"
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truncate -s %8 "$rawBootmemFile"
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# Reverse bytes
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objcopy --reverse-bytes=8 -F binary "$rawRamFile" "$ramFile"
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objcopy --reverse-bytes=8 -F binary "$rawBootmemFile" "$bootmemFile"
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rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile"
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rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile"
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echo "genInitMem.sh completed!"
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echo "genInitMem.sh completed!"
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@ -1,13 +0,0 @@
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SHELL = /bin/sh
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CFLAG = -Wall -g
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CC = gcc
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all: fixBinMem
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fixBinMem: fixBinMem.c
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${CC} ${CFLAGS} fixBinMem.c -o fixBinMem
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chmod +x fixBinMem
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clean:
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-rm -f fixBinMem
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@ -1,33 +0,0 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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int main(int argc, char *argv[]) {
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if (argc < 3){
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fprintf(stderr, "Expected 2 arguments: <raw GDB dump> <output binary>\n");
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exit(1);
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}
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char* rawGDBfilePath = argv[1];
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FILE* rawGDBfile;
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if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) {
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fprintf(stderr, "File not found: %s\n",rawGDBfilePath);
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exit(1);
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}
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char* outFilePath = argv[2];
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FILE* outFile = fopen(outFilePath,"w");
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uint64_t qemuWord;
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uint64_t verilogWord;
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int bytesReturned=0;
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do {
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bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile);
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verilogWord = (((qemuWord>>0 )&0xff)<<56 |
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((qemuWord>>8 )&0xff)<<48 |
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((qemuWord>>16)&0xff)<<40 |
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((qemuWord>>24)&0xff)<<32 |
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((qemuWord>>32)&0xff)<<24 |
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((qemuWord>>40)&0xff)<<16 |
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((qemuWord>>48)&0xff)<<8 |
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((qemuWord>>56)&0xff)<<0);
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fwrite(&verilogWord, 8, 1, outFile);
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} while(bytesReturned!=0);
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return 0;
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}
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