From 5684ae94412dbbd85d0cd90462a613b28e3244f3 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 29 Jan 2025 01:03:20 -0800 Subject: [PATCH 1/5] Updating MMU signal Propagation --- config/rv32gc/coverage.svh | 78 +++++++++++++++----------------- config/rv64gc/coverage.svh | 80 ++++++++++++++++----------------- sim/questa/wave.do | 21 +++++++++ testbench/common/wallyTracer.sv | 8 ++-- 4 files changed, 100 insertions(+), 87 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 20bddd5c0..d4898ff64 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -13,48 +13,44 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "I_coverage.svh" -`include "M_coverage.svh" -`include "F_coverage.svh" -`include "D_coverage.svh" -`include "Zba_coverage.svh" -`include "Zbb_coverage.svh" -`include "Zbc_coverage.svh" -`include "Zbs_coverage.svh" -`include "ZfaF_coverage.svh" -`include "ZfaD_coverage.svh" -`include "ZfaZfh_coverage.svh" -`include "Zfh_coverage.svh" -`include "ZfhD_coverage.svh" -// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled -`include "Zfhmin_coverage.svh" -// Note: Zmmul is a subset of M, so usually only one or the other would be used. -`include "Zmmul_coverage.svh" -`include "Zicond_coverage.svh" -`include "Zca_coverage.svh" -`include "Zcb_coverage.svh" -`include "ZcbM_coverage.svh" -`include "ZcbZbb_coverage.svh" -`include "Zcf_coverage.svh" -`include "Zcd_coverage.svh" -`include "Zicsr_coverage.svh" -`include "Zbkb_coverage.svh" -`include "Zbkc_coverage.svh" -`include "Zbkx_coverage.svh" -`include "Zknd_coverage.svh" -`include "Zkne_coverage.svh" -`include "Zknh_coverage.svh" -`include "Zaamo_coverage.svh" -`include "Zalrsc_coverage.svh" +// `include "I_coverage.svh" +// `include "M_coverage.svh" +// `include "F_coverage.svh" +// `include "D_coverage.svh" +// `include "Zba_coverage.svh" +// `include "Zbb_coverage.svh" +// `include "Zbc_coverage.svh" +// `include "Zbs_coverage.svh" +// `include "ZfaF_coverage.svh" +// `include "ZfaD_coverage.svh" +// `include "ZfaZfh_coverage.svh" +// `include "Zfh_coverage.svh" +// `include "ZfhD_coverage.svh" +// `include "Zicond_coverage.svh" +// `include "Zca_coverage.svh" +// `include "Zcb_coverage.svh" +// `include "ZcbM_coverage.svh" +// `include "ZcbZbb_coverage.svh" +// `include "Zcf_coverage.svh" +// `include "Zcd_coverage.svh" +// `include "Zicsr_coverage.svh" +// `include "Zbkb_coverage.svh" +// `include "Zbkc_coverage.svh" +// `include "Zbkx_coverage.svh" +// `include "Zknd_coverage.svh" +// `include "Zkne_coverage.svh" +// `include "Zknh_coverage.svh" +// `include "Zaamo_coverage.svh" +// `include "Zalrsc_coverage.svh" // Privileged extensions -`include "ZicsrM_coverage.svh" -`include "ZicsrF_coverage.svh" -`include "ZicsrU_coverage.svh" +// `include "ZicsrM_coverage.svh" +// `include "ZicsrF_coverage.svh" +// `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" -`include "EndianU_coverage.svh" -`include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" -`include "ExceptionsZc_coverage.svh" +// `include "EndianU_coverage.svh" +// `include "EndianM_coverage.svh" +// `include "EndianS_coverage.svh" +// `include "ExceptionsM_coverage.svh" +// `include "ExceptionsZc_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index fd8f11b04..9c0045ae3 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -13,50 +13,46 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "I_coverage.svh" -`include "M_coverage.svh" -`include "F_coverage.svh" -`include "D_coverage.svh" -`include "Zba_coverage.svh" -`include "Zbb_coverage.svh" -`include "Zbc_coverage.svh" -`include "Zbs_coverage.svh" -`include "ZfaF_coverage.svh" -`include "ZfaD_coverage.svh" -`include "ZfaZfh_coverage.svh" -`include "ZfhD_coverage.svh" -`include "Zfh_coverage.svh" -// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled -`include "Zfhmin_coverage.svh" -// Note: Zmmul is a subset of M, so usually only one or the other would be used. -`include "Zmmul_coverage.svh" -`include "Zicond_coverage.svh" -`include "Zca_coverage.svh" -`include "Zcb_coverage.svh" -`include "ZcbM_coverage.svh" -`include "ZcbZbb_coverage.svh" -`include "ZcbZba_coverage.svh" -`include "Zcd_coverage.svh" -`include "Zicsr_coverage.svh" -`include "Zbkb_coverage.svh" -`include "Zbkc_coverage.svh" -`include "Zbkx_coverage.svh" -`include "Zknd_coverage.svh" -`include "Zkne_coverage.svh" -`include "Zknh_coverage.svh" -`include "Zaamo_coverage.svh" -`include "Zalrsc_coverage.svh" +// `include "I_coverage.svh" +// `include "M_coverage.svh" +// `include "F_coverage.svh" +// `include "D_coverage.svh" +// `include "Zba_coverage.svh" +// `include "Zbb_coverage.svh" +// `include "Zbc_coverage.svh" +// `include "Zbs_coverage.svh" +// `include "ZfaF_coverage.svh" +// `include "ZfaD_coverage.svh" +// `include "ZfaZfh_coverage.svh" +// `include "ZfhD_coverage.svh" +// `include "Zfh_coverage.svh" +// `include "Zicond_coverage.svh" +// `include "Zca_coverage.svh" +// `include "Zcb_coverage.svh" +// `include "ZcbM_coverage.svh" +// `include "ZcbZbb_coverage.svh" +// `include "ZcbZba_coverage.svh" +// `include "Zcd_coverage.svh" +// `include "Zicsr_coverage.svh" +// `include "Zbkb_coverage.svh" +// `include "Zbkc_coverage.svh" +// `include "Zbkx_coverage.svh" +// `include "Zknd_coverage.svh" +// `include "Zkne_coverage.svh" +// `include "Zknh_coverage.svh" +// `include "Zaamo_coverage.svh" +// `include "Zalrsc_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" -`include "ZicsrM_coverage.svh" -`include "ZicsrF_coverage.svh" -`include "ZicsrU_coverage.svh" -`include "EndianU_coverage.svh" -`include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" -`include "ExceptionsZc_coverage.svh" -// `include "RV64VM_PMP_coverage.svh" +// `include "ZicsrM_coverage.svh" +// `include "ZicsrF_coverage.svh" +// `include "ZicsrU_coverage.svh" +// `include "EndianU_coverage.svh" +// `include "EndianM_coverage.svh" +// `include "EndianS_coverage.svh" +// `include "ExceptionsM_coverage.svh" +// `include "ExceptionsZc_coverage.svh" +`include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" diff --git a/sim/questa/wave.do b/sim/questa/wave.do index ee42a7065..115a40773 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -1,6 +1,27 @@ onerror {resume} quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd quietly WaveActivateNextPane {} 0 +add wave -position insertpoint sim:/testbench/wallyTracer/PCF +add wave -position insertpoint sim:/testbench/wallyTracer/PCD +add wave -position insertpoint sim:/testbench/wallyTracer/PCE +add wave -position insertpoint sim:/testbench/wallyTracer/PCM +add wave -position insertpoint sim:/testbench/wallyTracer/PCW +add wave -position insertpoint sim:/testbench/wallyTracer/GatedStallW +add wave -position insertpoint sim:/testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -position insertpoint sim:/testbench/wallyTracer/StallM +add wave -position insertpoint sim:/testbench/wallyTracer/StallW +add wave -position insertpoint sim:/testbench/wallyTracer/FlushW +add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iF +add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iD +add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iE +add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iM +add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iW +add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iM +add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iW +add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessM +add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessW +add wave -position insertpoint sim:/testbench/rvvi/valid +add wave -position insertpoint sim:/testbench/rvvi/csr[0][0][834] add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 093b72de2..bfb54a54e 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -364,25 +364,25 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); //for VM Verification flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU - flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IVAdrE, IVAdrM); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU - flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPAE, IPAM); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU - flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU + flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPTEE, IPTEM); //PTE for IMMU flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW From 54fd684d942a44715cfc387ee2eaa84e7385a4d6 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 29 Jan 2025 01:08:30 -0800 Subject: [PATCH 2/5] Restoring files --- config/rv32gc/coverage.svh | 78 +++++++++++++++++++------------------ config/rv64gc/coverage.svh | 80 ++++++++++++++++++++------------------ sim/questa/wave.do | 21 ---------- 3 files changed, 83 insertions(+), 96 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index d4898ff64..20bddd5c0 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -13,44 +13,48 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -// `include "I_coverage.svh" -// `include "M_coverage.svh" -// `include "F_coverage.svh" -// `include "D_coverage.svh" -// `include "Zba_coverage.svh" -// `include "Zbb_coverage.svh" -// `include "Zbc_coverage.svh" -// `include "Zbs_coverage.svh" -// `include "ZfaF_coverage.svh" -// `include "ZfaD_coverage.svh" -// `include "ZfaZfh_coverage.svh" -// `include "Zfh_coverage.svh" -// `include "ZfhD_coverage.svh" -// `include "Zicond_coverage.svh" -// `include "Zca_coverage.svh" -// `include "Zcb_coverage.svh" -// `include "ZcbM_coverage.svh" -// `include "ZcbZbb_coverage.svh" -// `include "Zcf_coverage.svh" -// `include "Zcd_coverage.svh" -// `include "Zicsr_coverage.svh" -// `include "Zbkb_coverage.svh" -// `include "Zbkc_coverage.svh" -// `include "Zbkx_coverage.svh" -// `include "Zknd_coverage.svh" -// `include "Zkne_coverage.svh" -// `include "Zknh_coverage.svh" -// `include "Zaamo_coverage.svh" -// `include "Zalrsc_coverage.svh" +`include "I_coverage.svh" +`include "M_coverage.svh" +`include "F_coverage.svh" +`include "D_coverage.svh" +`include "Zba_coverage.svh" +`include "Zbb_coverage.svh" +`include "Zbc_coverage.svh" +`include "Zbs_coverage.svh" +`include "ZfaF_coverage.svh" +`include "ZfaD_coverage.svh" +`include "ZfaZfh_coverage.svh" +`include "Zfh_coverage.svh" +`include "ZfhD_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" +// Note: Zmmul is a subset of M, so usually only one or the other would be used. +`include "Zmmul_coverage.svh" +`include "Zicond_coverage.svh" +`include "Zca_coverage.svh" +`include "Zcb_coverage.svh" +`include "ZcbM_coverage.svh" +`include "ZcbZbb_coverage.svh" +`include "Zcf_coverage.svh" +`include "Zcd_coverage.svh" +`include "Zicsr_coverage.svh" +`include "Zbkb_coverage.svh" +`include "Zbkc_coverage.svh" +`include "Zbkx_coverage.svh" +`include "Zknd_coverage.svh" +`include "Zkne_coverage.svh" +`include "Zknh_coverage.svh" +`include "Zaamo_coverage.svh" +`include "Zalrsc_coverage.svh" // Privileged extensions -// `include "ZicsrM_coverage.svh" -// `include "ZicsrF_coverage.svh" -// `include "ZicsrU_coverage.svh" +`include "ZicsrM_coverage.svh" +`include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" -// `include "EndianU_coverage.svh" -// `include "EndianM_coverage.svh" -// `include "EndianS_coverage.svh" -// `include "ExceptionsM_coverage.svh" -// `include "ExceptionsZc_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 9c0045ae3..fd8f11b04 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -13,46 +13,50 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -// `include "I_coverage.svh" -// `include "M_coverage.svh" -// `include "F_coverage.svh" -// `include "D_coverage.svh" -// `include "Zba_coverage.svh" -// `include "Zbb_coverage.svh" -// `include "Zbc_coverage.svh" -// `include "Zbs_coverage.svh" -// `include "ZfaF_coverage.svh" -// `include "ZfaD_coverage.svh" -// `include "ZfaZfh_coverage.svh" -// `include "ZfhD_coverage.svh" -// `include "Zfh_coverage.svh" -// `include "Zicond_coverage.svh" -// `include "Zca_coverage.svh" -// `include "Zcb_coverage.svh" -// `include "ZcbM_coverage.svh" -// `include "ZcbZbb_coverage.svh" -// `include "ZcbZba_coverage.svh" -// `include "Zcd_coverage.svh" -// `include "Zicsr_coverage.svh" -// `include "Zbkb_coverage.svh" -// `include "Zbkc_coverage.svh" -// `include "Zbkx_coverage.svh" -// `include "Zknd_coverage.svh" -// `include "Zkne_coverage.svh" -// `include "Zknh_coverage.svh" -// `include "Zaamo_coverage.svh" -// `include "Zalrsc_coverage.svh" +`include "I_coverage.svh" +`include "M_coverage.svh" +`include "F_coverage.svh" +`include "D_coverage.svh" +`include "Zba_coverage.svh" +`include "Zbb_coverage.svh" +`include "Zbc_coverage.svh" +`include "Zbs_coverage.svh" +`include "ZfaF_coverage.svh" +`include "ZfaD_coverage.svh" +`include "ZfaZfh_coverage.svh" +`include "ZfhD_coverage.svh" +`include "Zfh_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" +// Note: Zmmul is a subset of M, so usually only one or the other would be used. +`include "Zmmul_coverage.svh" +`include "Zicond_coverage.svh" +`include "Zca_coverage.svh" +`include "Zcb_coverage.svh" +`include "ZcbM_coverage.svh" +`include "ZcbZbb_coverage.svh" +`include "ZcbZba_coverage.svh" +`include "Zcd_coverage.svh" +`include "Zicsr_coverage.svh" +`include "Zbkb_coverage.svh" +`include "Zbkc_coverage.svh" +`include "Zbkx_coverage.svh" +`include "Zknd_coverage.svh" +`include "Zkne_coverage.svh" +`include "Zknh_coverage.svh" +`include "Zaamo_coverage.svh" +`include "Zalrsc_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" -// `include "ZicsrM_coverage.svh" -// `include "ZicsrF_coverage.svh" -// `include "ZicsrU_coverage.svh" -// `include "EndianU_coverage.svh" -// `include "EndianM_coverage.svh" -// `include "EndianS_coverage.svh" -// `include "ExceptionsM_coverage.svh" -// `include "ExceptionsZc_coverage.svh" -`include "RV64VM_PMP_coverage.svh" +`include "ZicsrM_coverage.svh" +`include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" +// `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 115a40773..ee42a7065 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -1,27 +1,6 @@ onerror {resume} quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd quietly WaveActivateNextPane {} 0 -add wave -position insertpoint sim:/testbench/wallyTracer/PCF -add wave -position insertpoint sim:/testbench/wallyTracer/PCD -add wave -position insertpoint sim:/testbench/wallyTracer/PCE -add wave -position insertpoint sim:/testbench/wallyTracer/PCM -add wave -position insertpoint sim:/testbench/wallyTracer/PCW -add wave -position insertpoint sim:/testbench/wallyTracer/GatedStallW -add wave -position insertpoint sim:/testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -position insertpoint sim:/testbench/wallyTracer/StallM -add wave -position insertpoint sim:/testbench/wallyTracer/StallW -add wave -position insertpoint sim:/testbench/wallyTracer/FlushW -add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iF -add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iD -add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iE -add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iM -add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iW -add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iM -add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iW -add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessM -add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessW -add wave -position insertpoint sim:/testbench/rvvi/valid -add wave -position insertpoint sim:/testbench/rvvi/csr[0][0][834] add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename From a303c694a344df83454ccbc15d0f01853b812378 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 30 Jan 2025 20:22:59 -0800 Subject: [PATCH 3/5] Always run installation CI in fresh docker image --- .github/workflows/install.yml | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 3cf9fd041..07f5ac3c5 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -37,67 +37,57 @@ jobs: include: # Ubuntu Installations - name: ubuntu-20.04 - os: ubuntu-20.04 - container: null + container: ubuntu:20.04 + imageFamily: debian regressionFail: true - name: ubuntu-22.04 - os: ubuntu-22.04 - container: null + container: ubuntu:22.04 + imageFamily: debian - name: ubuntu-24.04 - os: ubuntu-24.04 - container: null + container: ubuntu:24.04 + imageFamily: debian # Debian Installations - name: debian-12 - os: ubuntu-latest image: debian:12 imageFamily: debian - name: debian-11 - os: ubuntu-latest image: debian:11 imageFamily: debian # Red Hat Installations - name: rocky-8 - os: ubuntu-latest image: rockylinux:8 imageFamily: redhat regressionFail: true - name: rocky-9 - os: ubuntu-latest image: rockylinux:9 imageFamily: redhat - name: almalinux-8 - os: ubuntu-latest image: almalinux:8 imageFamily: redhat regressionFail: true - name: almalinux-9 - os: ubuntu-latest image: almalinux:9 imageFamily: redhat # SUSE Installations - name: opensuse-15.6 - os: ubuntu-latest image: opensuse/leap:15.6 imageFamily: suse # User level installation - name: user-install - os: ubuntu-latest image: null user: true # Custom location installation - name: custom-install - os: ubuntu-latest image: null riscv_path: /home/riscv # Custom location user level installation - name: custom-user-install - os: ubuntu-latest image: null user: true riscv_path: $HOME/riscv-toolchain # run on selected version of ubuntu or on ubuntu-latest with docker image - runs-on: ${{ matrix.os }} + runs-on: ubuntu-latest container: image: ${{ matrix.image }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash # Allow for connection with host From abb8f1a8fd604e27ecd677c630f1a650526fb0e8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 30 Jan 2025 20:26:23 -0800 Subject: [PATCH 4/5] Fix typo --- .github/workflows/install.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 07f5ac3c5..922d894c5 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -37,14 +37,14 @@ jobs: include: # Ubuntu Installations - name: ubuntu-20.04 - container: ubuntu:20.04 + image: ubuntu:20.04 imageFamily: debian regressionFail: true - name: ubuntu-22.04 - container: ubuntu:22.04 + image: ubuntu:22.04 imageFamily: debian - name: ubuntu-24.04 - container: ubuntu:24.04 + image: ubuntu:24.04 imageFamily: debian # Debian Installations - name: debian-12 From 9c2e16e2c150fc1879c4d0345a24059afe738443 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 3 Feb 2025 13:37:28 +0000 Subject: [PATCH 5/5] Bump addins/cvw-arch-verif from `44278d9` to `b31c5c2` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `44278d9` to `b31c5c2`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/44278d9a918dbc337ac214cd5dba5f71aa26dcfa...b31c5c25dafd9afa653f402014d8f8365472681a) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 44278d9a9..b31c5c25d 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 44278d9a918dbc337ac214cd5dba5f71aa26dcfa +Subproject commit b31c5c25dafd9afa653f402014d8f8365472681a