diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index afbf46761..d44e61f3c 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -180,6 +180,7 @@ module ifu (
   end else begin : bus
     localparam integer   WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN;
+    localparam integer   LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
     logic [LINELEN-1:0]  ReadDataLine;
     logic [LINELEN-1:0]  ICacheMemWriteData;
     logic [`PA_BITS-1:0] ICacheBusAdr;
@@ -187,11 +188,12 @@ module ifu (
     logic                save,restore;
     logic [31:0]         temp;
     
-    busdp #(WORDSPERLINE, LINELEN, 32) 
+    busdp #(WORDSPERLINE, LINELEN, 32, LOGWPL) 
     busdp(.clk, .reset,
           .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), 
-          .LSUBusRead(IFUBusRead), .LSUBusHWDATA(), .LSUBusSize(), 
+          .LSUBusRead(IFUBusRead), .LSUBusSize(), 
           .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
+          .WordCount(), .SelUncachedAdr(),
           .ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine),
           .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), 
           .DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),
diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv
index 9fc5887c2..dea671103 100644
--- a/pipelined/src/lsu/busdp.sv
+++ b/pipelined/src/lsu/busdp.sv
@@ -34,7 +34,7 @@
 
 `include "wally-config.vh"
 
-module busdp #(parameter WORDSPERLINE, parameter LINELEN, WORDLEN)
+module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL)
   (
   input logic                 clk, reset,
   // bus interface
@@ -42,14 +42,15 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN, WORDLEN)
   input logic                 LSUBusAck,
   output logic                LSUBusWrite,
   output logic                LSUBusRead,
-  output logic [`XLEN-1:0]    LSUBusHWDATA,
+//  output logic [`XLEN-1:0]    LSUBusHWDATA,
   output logic [2:0]          LSUBusSize, 
   input logic [2:0]           LSUFunct3M,
   output logic [`PA_BITS-1:0] LSUBusAdr,
-
+  output logic [LOGWPL-1:0]   WordCount,
+  output logic                SelUncachedAdr,
   // cache interface.
   input logic [`PA_BITS-1:0]  DCacheBusAdr,
-  input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
+  input var                   logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
   input logic                 DCacheFetchLine,
   input logic                 DCacheWriteLine,
   output logic                DCacheBusAck,
@@ -69,12 +70,10 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN, WORDLEN)
   
 
   localparam integer   WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0;
-  localparam integer   LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
 
-  logic                       SelUncachedAdr;
   logic [`XLEN-1:0]           PreLSUBusHWDATA;
   logic [`PA_BITS-1:0]        LocalLSUBusAdr;
-  logic [LOGWPL-1:0]          WordCount;
+
   genvar                      index;
 
   for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
@@ -85,9 +84,7 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN, WORDLEN)
 
   mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
   assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
-  assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; // only in lsu, not ifu
-  mux2 #(`XLEN) lsubushwdatamux(
-    .d0(PreLSUBusHWDATA), .d1(FinalAMOWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA));
+  //assign PreLSUBusHWDATA = ReadDataWordM;// ReadDataLineSetsM[WordCount]; // only in lsu, not ifu
   mux2 #(3) lsubussizemux(
     .d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize));
   mux2 #(WORDLEN) UnCachedDataMux(
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 18c0ccfb2..dcaf683f1 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -173,6 +173,8 @@ module lsu (
   logic [`XLEN-1:0]    FinalAMOWriteDataM, FinalWriteDataM;
   logic [`XLEN-1:0]    ReadDataWordM;
   logic [`XLEN-1:0]    ReadDataWordMuxM;
+  logic                SelUncachedAdr;
+  
 
   if (`DMEM == `MEM_TIM) begin : dtim
     dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
@@ -183,25 +185,37 @@ module lsu (
   end else begin : bus  
     localparam integer   WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN;
-    logic [`XLEN-1:0]    ReadDataLineSetsM [WORDSPERLINE-1:0];
+    localparam integer   LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
     logic [LINELEN-1:0]  ReadDataLineM;
     logic [LINELEN-1:0]  DCacheMemWriteData;
     logic [`PA_BITS-1:0] DCacheBusAdr;
     logic                DCacheWriteLine;
     logic                DCacheFetchLine;
     logic                DCacheBusAck;
-    logic                save,restore;
-
-    busdp #(WORDSPERLINE, LINELEN, `XLEN) busdp(
+    logic                save, restore;
+    logic [`PA_BITS-1:0] WordOffsetAddr;
+    logic                SelBus;
+    logic [LOGWPL-1:0]   WordCount;
+    logic [`XLEN-1:0]    ReadDataLineSetsM [WORDSPERLINE-1:0];
+    logic [`PA_BITS-1-`XLEN/8-LOGWPL:0] Pad;
+            
+    busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL) busdp(
       .clk, .reset,
-      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusHWDATA, .LSUBusSize, 
+      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
+                                                        .WordCount, .SelUncachedAdr,
       .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine,
       .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
       .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
       .BusStall, .BusCommittedM);
 
+    assign Pad = '0;
+    assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
+      mux2 #(`XLEN) lsubushwdatamux(
+    .d0(ReadDataWordM), .d1(FinalAMOWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA));
+
+
     subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
-      .clk, .reset, .PAdr(LSUPAdrM), .save, .restore,
+      .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
       .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM));
     
     if(`DMEM == `MEM_CACHE) begin : dcache