From 3ee29785a478d5eb07b69fec9b6d7f498d2edd9f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Dec 2021 15:56:18 -0600 Subject: [PATCH 01/15] Partial commit. Moved AMO, SWW, and SWR outside the dcache. Step 1 of separate the fetching logic from the caches. --- wally-pipelined/src/cache/dcache.sv | 95 ++++++++++++----------------- wally-pipelined/src/lsu/lsu.sv | 54 +++++++++++++++- 2 files changed, 91 insertions(+), 58 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 1936705e5..6fb3cca85 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -27,40 +27,45 @@ module dcache (input logic clk, - input logic reset, - input logic CPUBusy, + input logic reset, + input logic CPUBusy, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [6:0] Funct7M, - input logic [1:0] AtomicM, - input logic FlushDCacheM, - input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] MemPAdrM, // physical address - input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic FlushDCacheM, + input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] MemPAdrM, // physical address + input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. + + input logic [`XLEN-1:0] FinalWriteDataM, + output logic [`XLEN-1:0] ReadDataWordM, + output logic DCacheStall, + output logic CommittedM, + output logic DCacheMiss, + output logic DCacheAccess, - input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataM, - output logic DCacheStall, - output logic CommittedM, - output logic DCacheMiss, - output logic DCacheAccess, + // temp + output logic SelUncached, + output logic SelFlush, + output logic [`XLEN-1:0] DCacheMemWriteDataFirstWord, // inputs from TLB and PMA/P - input logic ExceptionM, - input logic PendingInterruptM, - input logic CacheableM, + input logic ExceptionM, + input logic PendingInterruptM, + input logic CacheableM, // from ptw - input logic IgnoreRequest, + input logic IgnoreRequest, // ahb side (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - (* mark_debug = "true" *)output logic AHBRead, - (* mark_debug = "true" *)output logic AHBWrite, - (* mark_debug = "true" *)input logic AHBAck, // from ahb - (* mark_debug = "true" *)input logic [`XLEN-1:0] HRDATA, // from ahb - (* mark_debug = "true" *)output logic [`XLEN-1:0] HWDATA, // to ahb - (* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM + (* mark_debug = "true" *)output logic AHBRead, + (* mark_debug = "true" *)output logic AHBWrite, + (* mark_debug = "true" *)input logic AHBAck, // from ahb + (* mark_debug = "true" *)input logic [`XLEN-1:0] HRDATA, // from ahb + (* mark_debug = "true" *)output logic [`XLEN-1:0] DC_HWDATA_FIXNAME, // to ahb + (* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM ); localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; @@ -90,8 +95,7 @@ module dcache logic CacheHit; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM; - logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; + logic [`XLEN-1:0] ReadDataWordMuxM; logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; @@ -105,7 +109,7 @@ module dcache logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; logic VictimDirty; - logic SelUncached; + logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; @@ -125,7 +129,6 @@ module dcache logic FlushWayCntEn; logic FlushWayCntRst; - logic SelFlush; logic VDWriteEnable; logic FetchCountFlag; @@ -220,16 +223,6 @@ module dcache assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), - .d1(DCacheMemWriteData[`XLEN-1:0]), - .s(SelUncached), - .y(ReadDataWordMuxM)); - - // finally swr - subwordread subwordread(.ReadDataWordMuxM, - .MemPAdrM(MemPAdrM[2:0]), - .Funct3M, - .ReadDataM); // Write Path CPU (IEU) side @@ -246,21 +239,6 @@ module dcache .s(SRAMBlockWriteEnableM), .y(SRAMWayWriteEnable)); - generate - if (`A_SUPPORTED) begin - logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]), - .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], FinalAMOWriteDataM); - end else - assign FinalAMOWriteDataM = WriteDataM; - endgenerate - - subwordwrite subwordwrite(.HRDATA(ReadDataWordM), - .HADDRD(MemPAdrM[2:0]), - .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), - .HWDATA(FinalWriteDataM)); mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), @@ -272,6 +250,7 @@ module dcache // register the fetch data from the next level of memory. // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. + generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer flopen #(`XLEN) fb(.clk(clk), @@ -281,6 +260,9 @@ module dcache end endgenerate + // temp + assign DCacheMemWriteDataFirstWord = DCacheMemWriteData[`XLEN-1:0]; + mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), @@ -294,7 +276,8 @@ module dcache assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; - assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM; + //assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM; + assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount]; assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index ed7a9fcbf..5db5a7568 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -300,6 +300,19 @@ module lsu // 2. cache `MEM_DCACHE // 3. wire pass-through assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0]; + + // temp + logic SelUncached; + logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; + logic [`XLEN-1:0] DC_HWDATA_FIXNAME; + logic SelFlush; + logic [`XLEN-1:0] ReadDataWordM; + logic [`XLEN-1:0] DCacheMemWriteDataFirstWord; + + // keep + logic [`XLEN-1:0] ReadDataWordMuxM; + + dcache dcache(.clk, .reset, .CPUBusy, .MemRWM(MemRWMtoDCache), @@ -309,21 +322,58 @@ module lsu .MemAdrE(MemAdrE_RENAME), .MemPAdrM, .VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed. - .WriteDataM, .ReadDataM, .DCacheStall, + .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .CommittedM(CommittedMfromDCache), .DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest, .PendingInterruptM(PendingInterruptMtoDCache), .CacheableM(CacheableMtoDCache), + // temp + .SelUncached, + .SelFlush, + .DCacheMemWriteDataFirstWord, + // AHB connection .AHBPAdr(DCtoAHBPAdrM), .AHBRead(DCtoAHBReadM), .AHBWrite(DCtoAHBWriteM), .AHBAck(DCfromAHBAck), - .HWDATA(DCtoAHBWriteData), + .DC_HWDATA_FIXNAME(DC_HWDATA_FIXNAME), .HRDATA(DCfromAHBReadData), .DCtoAHBSizeM ); + + mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), + .d1(DCacheMemWriteDataFirstWord), + .s(SelUncached), + .y(ReadDataWordMuxM)); + + // finally swr + subwordread subwordread(.ReadDataWordMuxM, + .MemPAdrM(MemPAdrM[2:0]), + .Funct3M(Funct3MtoDCache), + .ReadDataM); + + generate + if (`A_SUPPORTED) begin + logic [`XLEN-1:0] AMOResult; + amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3MtoDCache[1:0]), + .result(AMOResult)); + mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMtoDCache[1], FinalAMOWriteDataM); + end else + assign FinalAMOWriteDataM = WriteDataM; + endgenerate + + subwordwrite subwordwrite(.HRDATA(ReadDataWordM), + .HADDRD(MemPAdrM[2:0]), + .HSIZED({Funct3MtoDCache[2], 1'b0, Funct3MtoDCache[1:0]}), + .HWDATAIN(FinalAMOWriteDataM), + .HWDATA(FinalWriteDataM)); + + assign DCtoAHBWriteData = CacheableMtoDCache | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; + + + endmodule From 3e7ec1e9a2e8e437aebfe8fafc9589bc8638d780 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Dec 2021 16:45:49 -0600 Subject: [PATCH 02/15] Moved dcache fetch logic outside the dcache except for the fsm. --- wally-pipelined/src/cache/dcache.sv | 113 +++++++++------------------- wally-pipelined/src/lsu/lsu.sv | 79 ++++++++++++++++--- 2 files changed, 106 insertions(+), 86 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6fb3cca85..4b323ebf2 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -27,44 +27,50 @@ module dcache (input logic clk, - input logic reset, - input logic CPUBusy, + input logic reset, + input logic CPUBusy, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [6:0] Funct7M, - input logic [1:0] AtomicM, - input logic FlushDCacheM, - input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] MemPAdrM, // physical address - input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic FlushDCacheM, + input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] MemPAdrM, // physical address + input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. - input logic [`XLEN-1:0] FinalWriteDataM, - output logic [`XLEN-1:0] ReadDataWordM, - output logic DCacheStall, - output logic CommittedM, - output logic DCacheMiss, - output logic DCacheAccess, + input logic [`XLEN-1:0] FinalWriteDataM, + output logic [`XLEN-1:0] ReadDataWordM, + output logic DCacheStall, + output logic CommittedM, + output logic DCacheMiss, + output logic DCacheAccess, + + output logic [`PA_BITS-1:0] BasePAdrM, + output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], // temp - output logic SelUncached, - output logic SelFlush, - output logic [`XLEN-1:0] DCacheMemWriteDataFirstWord, + output logic SelUncached, + output logic SelFlush, + input logic FetchCountFlag, + output logic CntEn, + output logic CntReset, + + + input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, + // inputs from TLB and PMA/P - input logic ExceptionM, - input logic PendingInterruptM, - input logic CacheableM, + input logic ExceptionM, + input logic PendingInterruptM, + input logic CacheableM, // from ptw - input logic IgnoreRequest, + input logic IgnoreRequest, // ahb side - (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - (* mark_debug = "true" *)output logic AHBRead, - (* mark_debug = "true" *)output logic AHBWrite, - (* mark_debug = "true" *)input logic AHBAck, // from ahb - (* mark_debug = "true" *)input logic [`XLEN-1:0] HRDATA, // from ahb - (* mark_debug = "true" *)output logic [`XLEN-1:0] DC_HWDATA_FIXNAME, // to ahb + (* mark_debug = "true" *)output logic AHBRead, + (* mark_debug = "true" *)output logic AHBWrite, + (* mark_debug = "true" *)input logic AHBAck, // from ahb (* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM ); @@ -80,23 +86,19 @@ module dcache localparam integer LOGWPL = $clog2(WORDSPERLINE); localparam integer LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer FetchCountThreshold = WORDSPERLINE - 1; localparam integer FlushAdrThreshold = NUMLINES - 1; logic [1:0] SelAdrM; logic [INDEXLEN-1:0] RAdr; logic [INDEXLEN-1:0] WAdr; logic [BLOCKLEN-1:0] SRAMWriteData; - logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValid, ClearValid; logic SetDirty, ClearDirty; logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; logic [BLOCKLEN-1:0] ReadDataBlockM; - logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordMuxM; - logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SRAMWordWriteEnableM; @@ -112,9 +114,6 @@ module dcache logic [2**LOGWPL-1:0] MemPAdrDecodedW; - logic [`PA_BITS-1:0] BasePAdrM; - logic [OFFSETLEN-1:0] BasePAdrOffsetM; - logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; @@ -131,9 +130,6 @@ module dcache logic VDWriteEnable; - logic FetchCountFlag; - logic CntEn; - logic CntReset; logic SelEvict; logic LRUWriteEn; @@ -246,49 +242,14 @@ module dcache .s(SRAMBlockWriteEnableM), .y(SRAMWriteData)); - // Bus Side logic - // register the fetch data from the next level of memory. - // This register should be necessary for timing. There is no register in the uncore or - // ahblite controller between the memories and this cache. - - generate - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - flopen #(`XLEN) fb(.clk(clk), - .en(AHBAck & AHBRead & (index == FetchCount)), - .d(HRDATA), - .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); - end - endgenerate - - // temp - assign DCacheMemWriteDataFirstWord = DCacheMemWriteData[`XLEN-1:0]; - + + //assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM; mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .s({SelFlush, SelEvict}), .y(BasePAdrM)); - // if not cacheable the offset bits needs to be sent to the EBU. - // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. - assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; - assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; - - assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; - - //assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM; - assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount]; - - assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); - - flopenr #(LOGWPL) - FetchCountReg(.clk(clk), - .reset(reset | CntReset), - .en(CntEn), - .d(NextFetchCount), - .q(FetchCount)); - - assign NextFetchCount = FetchCount + 1'b1; // flush address and way generation. flopenr #(INDEXLEN) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 5db5a7568..955480233 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -63,11 +63,11 @@ module lsu output logic StoreMisalignedFaultM, StoreAccessFaultM, // connect to ahb - output logic [`PA_BITS-1:0] DCtoAHBPAdrM, +(* mark_debug = "true" *) output logic [`PA_BITS-1:0] DCtoAHBPAdrM, output logic DCtoAHBReadM, output logic DCtoAHBWriteM, input logic DCfromAHBAck, - input logic [`XLEN-1:0] DCfromAHBReadData, +(* mark_debug = "true" *) input logic [`XLEN-1:0] DCfromAHBReadData, output logic [`XLEN-1:0] DCtoAHBWriteData, output logic [2:0] DCtoAHBSizeM, @@ -301,18 +301,40 @@ module lsu // 3. wire pass-through assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0]; + localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN; + localparam integer LOGWPL = $clog2(WORDSPERLINE); + localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; + + localparam integer FetchCountThreshold = WORDSPERLINE - 1; + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + // temp logic SelUncached; + logic FetchCountFlag; + logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; - logic [`XLEN-1:0] DC_HWDATA_FIXNAME; + (* mark_debug = "true" *) logic [`XLEN-1:0] DC_HWDATA_FIXNAME; logic SelFlush; logic [`XLEN-1:0] ReadDataWordM; - logic [`XLEN-1:0] DCacheMemWriteDataFirstWord; + logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData; // keep logic [`XLEN-1:0] ReadDataWordMuxM; + + + logic [LOGWPL-1:0] FetchCount, NextFetchCount; + logic [`PA_BITS-1:0] BasePAdrMaskedM; + logic [OFFSETLEN-1:0] BasePAdrOffsetM; + + logic CntEn; + logic CntReset; + logic [`PA_BITS-1:0] BasePAdrM; + logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0]; - + + + dcache dcache(.clk, .reset, .CPUBusy, .MemRWM(MemRWMtoDCache), @@ -328,24 +350,26 @@ module lsu .PendingInterruptM(PendingInterruptMtoDCache), .CacheableM(CacheableMtoDCache), + .BasePAdrM, + .ReadDataBlockSetsM, // temp .SelUncached, .SelFlush, - .DCacheMemWriteDataFirstWord, + .DCacheMemWriteData, + .FetchCountFlag, + .CntEn, + .CntReset, // AHB connection - .AHBPAdr(DCtoAHBPAdrM), .AHBRead(DCtoAHBReadM), .AHBWrite(DCtoAHBWriteM), .AHBAck(DCfromAHBAck), - .DC_HWDATA_FIXNAME(DC_HWDATA_FIXNAME), - .HRDATA(DCfromAHBReadData), .DCtoAHBSizeM ); mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), - .d1(DCacheMemWriteDataFirstWord), + .d1(DCacheMemWriteData[`XLEN-1:0]), .s(SelUncached), .y(ReadDataWordMuxM)); @@ -372,8 +396,43 @@ module lsu .HWDATA(FinalWriteDataM)); assign DCtoAHBWriteData = CacheableMtoDCache | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; + + + // Bus Side logic + // register the fetch data from the next level of memory. + // This register should be necessary for timing. There is no register in the uncore or + // ahblite controller between the memories and this cache. + + genvar index; + generate + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + flopen #(`XLEN) fb(.clk(clk), + .en(DCfromAHBAck & DCtoAHBReadM & (index == FetchCount)), + .d(DCfromAHBReadData), + .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); + end + endgenerate + + + // if not cacheable the offset bits needs to be sent to the EBU. + // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. + assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; + assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; + assign DCtoAHBPAdrM = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; + assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount]; + + assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); + + flopenr #(LOGWPL) + FetchCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); + + assign NextFetchCount = FetchCount + 1'b1; endmodule From 44b63fc0bafee0277ca7d2d9fdd2b3531703a617 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Dec 2021 18:12:59 -0600 Subject: [PATCH 03/15] First cut at moving the dcache bus interface into the LSU. Regression test does not run and there is a lot of cleanup to do. --- wally-pipelined/regression/wave.do | 304 ++++++++++++------------- wally-pipelined/src/cache/dcache.sv | 82 ++++--- wally-pipelined/src/cache/dcachefsm.sv | 18 +- wally-pipelined/src/lsu/lsu.sv | 235 +++++++++++++++---- 4 files changed, 398 insertions(+), 241 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 8f0ed0724..49413e300 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -203,163 +203,151 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width -add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr -add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable @@ -487,8 +475,16 @@ add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB add wave -noupdate /testbench/dut/hart/ifu/temp add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM +add wave -noupdate /testbench/dut/hart/lsu/BusCurrState +add wave -noupdate /testbench/dut/hart/lsu/BasePAdrM +add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBPAdrM +add wave -noupdate /testbench/dut/hart/lsu/FetchCountFlag +add wave -noupdate /testbench/dut/hart/lsu/FetchCount +add wave -noupdate /testbench/dut/hart/lsu/DCfromAHBAck +add wave -noupdate /testbench/dut/hart/lsu/BUSACK +add wave -noupdate /testbench/dut/hart/lsu/DCFetchLine TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {26638 ns} 0} +WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {2947 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -504,4 +500,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {26532 ns} {26750 ns} +WaveRestoreZoom {2791 ns} {3081 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 4b323ebf2..145375612 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -27,50 +27,57 @@ module dcache (input logic clk, - input logic reset, - input logic CPUBusy, + input logic reset, + input logic CPUBusy, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [6:0] Funct7M, - input logic [1:0] AtomicM, - input logic FlushDCacheM, - input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] MemPAdrM, // physical address - input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic FlushDCacheM, + input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] MemPAdrM, // physical address + input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. - input logic [`XLEN-1:0] FinalWriteDataM, - output logic [`XLEN-1:0] ReadDataWordM, - output logic DCacheStall, - output logic CommittedM, - output logic DCacheMiss, - output logic DCacheAccess, + input logic [`XLEN-1:0] FinalWriteDataM, + output logic [`XLEN-1:0] ReadDataWordM, + output logic DCacheStall, + output logic CommittedM, + output logic DCacheMiss, + output logic DCacheAccess, - output logic [`PA_BITS-1:0] BasePAdrM, - output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], + output logic DCWriteLine, + output logic DCFetchLine, + input logic BUSACK, + + + output logic [`PA_BITS-1:0] BasePAdrM, + output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], // temp - output logic SelUncached, - output logic SelFlush, - input logic FetchCountFlag, - output logic CntEn, - output logic CntReset, + //output logic SelUncached, + output logic SelFlush, + //input logic FetchCountFlag, + //output logic CntEn, + //output logic CntReset, input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, // inputs from TLB and PMA/P - input logic ExceptionM, - input logic PendingInterruptM, - input logic CacheableM, + input logic ExceptionM, + input logic PendingInterruptM, + input logic CacheableM, // from ptw - input logic IgnoreRequest, + input logic IgnoreRequest, // ahb side - (* mark_debug = "true" *)output logic AHBRead, - (* mark_debug = "true" *)output logic AHBWrite, - (* mark_debug = "true" *)input logic AHBAck, // from ahb +/* -----\/----- EXCLUDED -----\/----- + (* mark_debug = "true" *)output logic AHBRead, + (* mark_debug = "true" *)output logic AHBWrite, + -----/\----- EXCLUDED -----/\----- */ + (* mark_debug = "true" *)input logic AHBAck, // from ahb (* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM ); @@ -286,6 +293,9 @@ module dcache dcachefsm dcachefsm(.clk, .reset, + .DCFetchLine, + .DCWriteLine, + .BUSACK, .MemRWM, .AtomicM, .ExceptionM, @@ -295,24 +305,24 @@ module dcache .IgnoreRequest, .AHBAck, // from ahb .CacheHit, - .FetchCountFlag, + .FetchCountFlag(1'b0), .VictimDirty, .DCacheStall, .CommittedM, .DCacheMiss, .DCacheAccess, - .AHBRead, - .AHBWrite, + .AHBRead(), + .AHBWrite(), .SelAdrM, - .CntEn, + .CntEn(), .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, .SRAMBlockWriteEnableM, - .CntReset, - .SelUncached, + .CntReset(), + .SelUncached(), .SelEvict, .SelFlush, .FlushAdrCntEn, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index f11b3c3e5..1279feb36 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -57,6 +57,10 @@ module dcachefsm output logic AHBRead, output logic AHBWrite, + output logic DCWriteLine, + output logic DCFetchLine, + input logic BUSACK, + // dcache internals output logic [1:0] SelAdrM, output logic CntEn, @@ -142,6 +146,8 @@ module dcachefsm FlushWayCntRst = 1'b0; VDWriteEnable = 1'b0; NextState = STATE_READY; + DCFetchLine = 1'b0; + DCWriteLine = 1'b0; case (CurrState) STATE_READY: begin @@ -227,6 +233,7 @@ module dcachefsm NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; + DCFetchLine = 1'b1; end // uncached write else if(MemRWM[0] & ~CacheableM) begin @@ -252,7 +259,8 @@ module dcachefsm SelAdrM = 2'b10; CommittedM = 1'b1; - if (FetchCountFlag & AHBAck) begin + //if (FetchCountFlag & AHBAck) begin + if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; end else begin NextState = STATE_MISS_FETCH_WDV; @@ -266,6 +274,7 @@ module dcachefsm CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; + DCWriteLine = 1'b1; end else begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end @@ -346,7 +355,8 @@ module dcachefsm SelAdrM = 2'b10; CommittedM = 1'b1; SelEvict = 1'b1; - if(FetchCountFlag & AHBAck) begin + //if(FetchCountFlag & AHBAck) begin + if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin NextState = STATE_MISS_EVICT_DIRTY; @@ -442,6 +452,7 @@ module dcachefsm NextState = STATE_FLUSH_WRITE_BACK; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; + DCWriteLine = 1'b1; end else if (FlushAdrFlag) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -459,7 +470,8 @@ module dcachefsm CommittedM = 1'b1; SelFlush = 1'b1; PreCntEn = 1'b1; - if(FetchCountFlag & AHBAck) begin + //if(FetchCountFlag & AHBAck) begin + if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin NextState = STATE_FLUSH_WRITE_BACK; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 955480233..97f4c9d40 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -118,11 +118,14 @@ module lsu logic CommittedMfromDCache; + logic CommittedMfromBus; logic PendingInterruptMtoDCache; logic WalkerPageFaultM; logic AnyCPUReqM; logic MemAfterIWalkDone; + logic BusStall; + typedef enum {STATE_T0_READY, STATE_T0_REPLAY, @@ -132,7 +135,7 @@ module lsu STATE_T5_ITLB_MISS, STATE_T7_DITLB_MISS} statetype; - statetype CurrState, NextState; + statetype InterlockCurrState, InterlockNextState; logic InterlockStall; logic SelReplayCPURequest; logic WalkerInstrPageFaultRaw; @@ -141,32 +144,32 @@ module lsu assign AnyCPUReqM = (|MemRWM) | (|AtomicM); always_ff @(posedge clk) - if (reset) CurrState <= #1 STATE_T0_READY; - else CurrState <= #1 NextState; + if (reset) InterlockCurrState <= #1 STATE_T0_READY; + else InterlockCurrState <= #1 InterlockNextState; always_comb begin - case(CurrState) - STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T3_DTLB_MISS; - else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) NextState = STATE_T4_ITLB_MISS; - else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) NextState = STATE_T5_ITLB_MISS; - else if(ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T7_DITLB_MISS; - else NextState = STATE_T0_READY; - STATE_T0_REPLAY: if(DCacheStall) NextState = STATE_T0_REPLAY; - else NextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) NextState = STATE_T0_READY; - else if(DTLBWriteM) NextState = STATE_T0_REPLAY; - else NextState = STATE_T3_DTLB_MISS; - STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) NextState = STATE_T0_READY; - else NextState = STATE_T4_ITLB_MISS; - STATE_T5_ITLB_MISS: if(ITLBWriteF) NextState = STATE_T0_REPLAY; - else if(WalkerInstrPageFaultRaw) NextState = STATE_T0_FAULT_REPLAY; - else NextState = STATE_T5_ITLB_MISS; - STATE_T0_FAULT_REPLAY: if(DCacheStall) NextState = STATE_T0_FAULT_REPLAY; - else NextState = STATE_T0_READY; - STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) NextState = STATE_T0_READY; - else if(DTLBWriteM) NextState = STATE_T5_ITLB_MISS; - else NextState = STATE_T7_DITLB_MISS; - default: NextState = STATE_T0_READY; + case(InterlockCurrState) + STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; + else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; + else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; + else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; + else InterlockNextState = STATE_T0_READY; + STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T0_READY; + STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) InterlockNextState = STATE_T0_READY; + else if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T3_DTLB_MISS; + STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) InterlockNextState = STATE_T0_READY; + else InterlockNextState = STATE_T4_ITLB_MISS; + STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; + else if(WalkerInstrPageFaultRaw) InterlockNextState = STATE_T0_FAULT_REPLAY; + else InterlockNextState = STATE_T5_ITLB_MISS; + STATE_T0_FAULT_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_FAULT_REPLAY; + else InterlockNextState = STATE_T0_READY; + STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) InterlockNextState = STATE_T0_READY; + else if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; + else InterlockNextState = STATE_T7_DITLB_MISS; + default: InterlockNextState = STATE_T0_READY; endcase end // always_comb @@ -174,15 +177,15 @@ module lsu /* -----\/----- EXCLUDED -----\/----- // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. - assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) | - (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); + assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | + (InterlockCurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (InterlockCurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) | + (InterlockCurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (InterlockCurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); -----/\----- EXCLUDED -----/\----- */ always_comb begin InterlockStall = 1'b0; - case(CurrState) + case(InterlockCurrState) STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1; STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1; @@ -195,14 +198,14 @@ module lsu // When replaying CPU memory request after PTW select the IEUAdrM for correct address. - assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY); - assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) | - (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS); - assign IgnoreRequest = (CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | - ((CurrState == STATE_T0_REPLAY | CurrState == STATE_T0_FAULT_REPLAY) + assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY) | (InterlockNextState == STATE_T0_FAULT_REPLAY); + assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); + assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | + ((InterlockCurrState == STATE_T0_REPLAY | InterlockCurrState == STATE_T0_FAULT_REPLAY) & (ExceptionM | PendingInterruptM)); - assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY; + assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | InterlockCurrState == STATE_T0_FAULT_REPLAY; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -218,7 +221,7 @@ module lsu .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), .WalkerLoadPageFaultM, .WalkerStorePageFaultM); - assign LSUStall = DCacheStall | InterlockStall; + assign LSUStall = DCacheStall | InterlockStall | BusStall; assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; @@ -239,7 +242,7 @@ module lsu assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; assign CPUBusy = SelHPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache; + assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache | CommittedMfromBus; assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM; @@ -268,7 +271,7 @@ module lsu // Move generate from lrsc to outside this module. - assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; + assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & InterlockCurrState != STATE_STALLED; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, .SquashSCW, .MemRWMtoDCache); @@ -327,14 +330,16 @@ module lsu logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [OFFSETLEN-1:0] BasePAdrOffsetM; - logic CntEn; + logic CntEn, PreCntEn; logic CntReset; logic [`PA_BITS-1:0] BasePAdrM; logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0]; - + logic DCWriteLine; + logic DCFetchLine; + logic BUSACK; dcache dcache(.clk, .reset, .CPUBusy, .MemRWM(MemRWMtoDCache), @@ -353,17 +358,18 @@ module lsu .BasePAdrM, .ReadDataBlockSetsM, // temp - .SelUncached, + //.SelUncached, .SelFlush, .DCacheMemWriteData, - .FetchCountFlag, - .CntEn, - .CntReset, + //.FetchCountFlag, + //.CntEn, + //.CntReset, + .DCFetchLine, + .DCWriteLine, + .BUSACK, // AHB connection - .AHBRead(DCtoAHBReadM), - .AHBWrite(DCtoAHBWriteM), - .AHBAck(DCfromAHBAck), + .AHBAck(1'b0), .DCtoAHBSizeM ); @@ -424,7 +430,8 @@ module lsu assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount]; assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); - + assign CntEn = PreCntEn & DCfromAHBAck; + flopenr #(LOGWPL) FetchCountReg(.clk(clk), .reset(reset | CntReset), @@ -434,5 +441,137 @@ module lsu assign NextFetchCount = FetchCount + 1'b1; + typedef enum {STATE_BUS_READY, + STATE_BUS_FETCH_WDV, + STATE_BUS_FETCH_DONE, + STATE_BUS_EVICT_DIRTY, + STATE_BUS_WRITE_CACHE_BLOCK, + STATE_BUS_UNCACHED_WRITE, + STATE_BUS_UNCACHED_WRITE_DONE, + STATE_BUS_UNCACHED_READ, + STATE_BUS_UNCACHED_READ_DONE} busstatetype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + always_ff @(posedge clk) + if (reset) BusCurrState <= #1 STATE_BUS_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + BusNextState = STATE_BUS_READY; + CntReset = 1'b0; + BusStall = 1'b0; + PreCntEn = 1'b0; + DCtoAHBWriteM = 1'b0; + DCtoAHBReadM = 1'b0; + CommittedMfromBus = 1'b0; + BUSACK = 1'b0; + SelUncached = 1'b0; + + case(BusCurrState) + STATE_BUS_READY: begin + // uncache write + if(MemRWMtoDCache[0] & ~CacheableMtoDCache) begin + BusNextState = STATE_BUS_UNCACHED_WRITE; + CntReset = 1'b1; + BusStall = 1'b1; + DCtoAHBWriteM = 1'b1; + end + // uncached read + else if(MemRWMtoDCache[1] & ~CacheableMtoDCache) begin + BusNextState = STATE_BUS_UNCACHED_READ; + CntReset = 1'b1; + BusStall = 1'b1; + DCtoAHBReadM = 1'b1; + end + // D$ Fetch Line + else if(DCFetchLine) begin + BusNextState = STATE_BUS_FETCH_WDV; + CntReset = 1'b1; + BusStall = 1'b1; + end + // D$ Write Line + else if(DCWriteLine) begin + BusNextState = STATE_BUS_EVICT_DIRTY; + CntReset = 1'b1; + BusStall = 1'b1; + end + end + + STATE_BUS_UNCACHED_WRITE : begin + BusStall = 1'b1; + DCtoAHBWriteM = 1'b1; + CommittedMfromBus = 1'b1; + if(DCfromAHBAck) begin + BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; + end else begin + BusNextState = STATE_BUS_UNCACHED_WRITE; + end + end + + STATE_BUS_UNCACHED_READ: begin + BusStall = 1'b1; + DCtoAHBReadM = 1'b1; + CommittedMfromBus = 1'b1; + if(DCfromAHBAck) begin + BusNextState = STATE_BUS_UNCACHED_READ_DONE; + end else begin + BusNextState = STATE_BUS_UNCACHED_READ; + end + end + + STATE_BUS_UNCACHED_WRITE_DONE: begin + CommittedMfromBus = 1'b1; + BusNextState = STATE_BUS_READY; + end + + STATE_BUS_UNCACHED_READ_DONE: begin + CommittedMfromBus = 1'b1; + SelUncached = 1'b1; + end + + STATE_BUS_FETCH_WDV: begin + BusStall = 1'b1; + PreCntEn = 1'b1; + DCtoAHBReadM = 1'b1; + CommittedMfromBus = 1'b1; + + if (FetchCountFlag & DCfromAHBAck) begin + BusNextState = STATE_BUS_FETCH_DONE; + end else begin + BusNextState = STATE_BUS_FETCH_WDV; + end + end + + STATE_BUS_FETCH_DONE: begin + BusStall = 1'b1; + CntReset = 1'b1; + CommittedMfromBus = 1'b1; + BusNextState = STATE_BUS_READY; + BUSACK = 1'b1; + end + + STATE_BUS_EVICT_DIRTY: begin + BusStall = 1'b1; + PreCntEn = 1'b1; + DCtoAHBWriteM = 1'b1; + CommittedMfromBus = 1'b1; + if(FetchCountFlag & DCfromAHBAck) begin + BusNextState = STATE_BUS_WRITE_CACHE_BLOCK; + end else begin + BusNextState = STATE_BUS_EVICT_DIRTY; + end + end + + STATE_BUS_WRITE_CACHE_BLOCK: begin + BusStall = 1'b1; + CntReset = 1'b1; + CommittedMfromBus = 1'b1; + BusNextState = STATE_BUS_READY; + BUSACK = 1'b1; + end + endcase + end + endmodule From d6960da90e278794f02675891c1a06b69511c825 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 11:18:47 -0600 Subject: [PATCH 04/15] Moved all bus logic outside the dcache. Still needs cleanup. --- wally-pipelined/src/lsu/lsu.sv | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 97f4c9d40..7b84e1427 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -470,6 +470,9 @@ module lsu case(BusCurrState) STATE_BUS_READY: begin + if(IgnoreRequest) begin + BusNextState = STATE_BUS_READY; + end else // uncache write if(MemRWMtoDCache[0] & ~CacheableMtoDCache) begin BusNextState = STATE_BUS_UNCACHED_WRITE; @@ -537,39 +540,25 @@ module lsu CommittedMfromBus = 1'b1; if (FetchCountFlag & DCfromAHBAck) begin - BusNextState = STATE_BUS_FETCH_DONE; + BusNextState = STATE_BUS_READY; + BUSACK = 1'b1; end else begin BusNextState = STATE_BUS_FETCH_WDV; end end - STATE_BUS_FETCH_DONE: begin - BusStall = 1'b1; - CntReset = 1'b1; - CommittedMfromBus = 1'b1; - BusNextState = STATE_BUS_READY; - BUSACK = 1'b1; - end - STATE_BUS_EVICT_DIRTY: begin BusStall = 1'b1; PreCntEn = 1'b1; DCtoAHBWriteM = 1'b1; CommittedMfromBus = 1'b1; if(FetchCountFlag & DCfromAHBAck) begin - BusNextState = STATE_BUS_WRITE_CACHE_BLOCK; + BusNextState = STATE_BUS_READY; + BUSACK = 1'b1; end else begin BusNextState = STATE_BUS_EVICT_DIRTY; end end - - STATE_BUS_WRITE_CACHE_BLOCK: begin - BusStall = 1'b1; - CntReset = 1'b1; - CommittedMfromBus = 1'b1; - BusNextState = STATE_BUS_READY; - BUSACK = 1'b1; - end endcase end From 77e8ba619e5b455148fd84bc2fbea6dae595ff93 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 11:29:16 -0600 Subject: [PATCH 05/15] Minor dcache cleanup. --- wally-pipelined/src/cache/dcache.sv | 13 ---- wally-pipelined/src/cache/dcachefsm.sv | 97 +------------------------- wally-pipelined/src/lsu/lsu.sv | 15 ++-- 3 files changed, 5 insertions(+), 120 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 145375612..fa2b20469 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -55,13 +55,7 @@ module dcache output logic [`PA_BITS-1:0] BasePAdrM, output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], - // temp - //output logic SelUncached, output logic SelFlush, - //input logic FetchCountFlag, - //output logic CntEn, - //output logic CntReset, - input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, @@ -303,26 +297,19 @@ module dcache .CPUBusy, .CacheableM, .IgnoreRequest, - .AHBAck, // from ahb .CacheHit, - .FetchCountFlag(1'b0), .VictimDirty, .DCacheStall, .CommittedM, .DCacheMiss, .DCacheAccess, - .AHBRead(), - .AHBWrite(), .SelAdrM, - .CntEn(), .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, .SRAMBlockWriteEnableM, - .CntReset(), - .SelUncached(), .SelEvict, .SelFlush, .FlushAdrCntEn, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 1279feb36..e49c23db7 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -40,10 +40,9 @@ module dcachefsm // hptw inputs input logic IgnoreRequest, // Bus inputs - input logic AHBAck, // from ahb + input logic BUSACK, // dcache internals input logic CacheHit, - input logic FetchCountFlag, input logic VictimDirty, input logic FlushAdrFlag, @@ -54,24 +53,18 @@ module dcachefsm output logic DCacheMiss, output logic DCacheAccess, // Bus outputs - output logic AHBRead, - output logic AHBWrite, output logic DCWriteLine, output logic DCFetchLine, - input logic BUSACK, // dcache internals output logic [1:0] SelAdrM, - output logic CntEn, output logic SetValid, output logic ClearValid, output logic SetDirty, output logic ClearDirty, output logic SRAMWordWriteEnableM, output logic SRAMBlockWriteEnableM, - output logic CntReset, - output logic SelUncached, output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, @@ -83,7 +76,6 @@ module dcachefsm ); - logic PreCntEn; logic AnyCPUReqM; typedef enum {STATE_READY, @@ -96,11 +88,6 @@ module dcachefsm STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, - STATE_UNCACHED_WRITE, - STATE_UNCACHED_WRITE_DONE, - STATE_UNCACHED_READ, - STATE_UNCACHED_READ_DONE, - STATE_CPU_BUSY, STATE_CPU_BUSY_FINISH_AMO, @@ -111,7 +98,6 @@ module dcachefsm (* mark_debug = "true" *) statetype CurrState, NextState; assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign CntEn = PreCntEn & AHBAck; // outputs for the performance counters. assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY; @@ -125,18 +111,13 @@ module dcachefsm always_comb begin DCacheStall = 1'b0; SelAdrM = 2'b00; - PreCntEn = 1'b0; SetValid = 1'b0; ClearValid = 1'b0; SetDirty = 1'b0; ClearDirty = 1'b0; SRAMWordWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0; - CntReset = 1'b0; - AHBRead = 1'b0; - AHBWrite = 1'b0; CommittedM = 1'b0; - SelUncached = 1'b0; SelEvict = 1'b0; LRUWriteEn = 1'b0; SelFlush = 1'b0; @@ -152,10 +133,7 @@ module dcachefsm case (CurrState) STATE_READY: begin - CntReset = 1'b0; DCacheStall = 1'b0; - AHBRead = 1'b0; - AHBWrite = 1'b0; SelAdrM = 2'b00; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; @@ -231,35 +209,17 @@ module dcachefsm // read or write miss valid cached else if((|MemRWM) & CacheableM & ~CacheHit) begin NextState = STATE_MISS_FETCH_WDV; - CntReset = 1'b1; DCacheStall = 1'b1; DCFetchLine = 1'b1; end - // uncached write - else if(MemRWM[0] & ~CacheableM) begin - NextState = STATE_UNCACHED_WRITE; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBWrite = 1'b1; - end - // uncached read - else if(MemRWM[1] & ~CacheableM) begin - NextState = STATE_UNCACHED_READ; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBRead = 1'b1; - end else NextState = STATE_READY; end STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; SelAdrM = 2'b10; CommittedM = 1'b1; - //if (FetchCountFlag & AHBAck) begin if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; end else begin @@ -270,7 +230,6 @@ module dcachefsm STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CntReset = 1'b1; CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; @@ -350,12 +309,9 @@ module dcachefsm STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBWrite = 1'b1; SelAdrM = 2'b10; CommittedM = 1'b1; SelEvict = 1'b1; - //if(FetchCountFlag & AHBAck) begin if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin @@ -393,53 +349,6 @@ module dcachefsm end end - STATE_UNCACHED_WRITE : begin - DCacheStall = 1'b1; - AHBWrite = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_UNCACHED_WRITE_DONE; - end else begin - NextState = STATE_UNCACHED_WRITE; - end - end - - STATE_UNCACHED_READ: begin - DCacheStall = 1'b1; - AHBRead = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_UNCACHED_READ_DONE; - end else begin - NextState = STATE_UNCACHED_READ; - end - end - - STATE_UNCACHED_WRITE_DONE: begin - CommittedM = 1'b1; - SelAdrM = 2'b00; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; - end - else begin - NextState = STATE_READY; - end - end - - STATE_UNCACHED_READ_DONE: begin - CommittedM = 1'b1; - SelUncached = 1'b1; - SelAdrM = 2'b00; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; - end - else begin - NextState = STATE_READY; - end - end - STATE_FLUSH: begin DCacheStall = 1'b1; CommittedM = 1'b1; @@ -447,7 +356,6 @@ module dcachefsm SelFlush = 1'b1; FlushAdrCntEn = 1'b1; FlushWayCntEn = 1'b1; - CntReset = 1'b1; if(VictimDirty) begin NextState = STATE_FLUSH_WRITE_BACK; FlushAdrCntEn = 1'b0; @@ -465,12 +373,9 @@ module dcachefsm STATE_FLUSH_WRITE_BACK: begin DCacheStall = 1'b1; - AHBWrite = 1'b1; SelAdrM = 2'b11; CommittedM = 1'b1; SelFlush = 1'b1; - PreCntEn = 1'b1; - //if(FetchCountFlag & AHBAck) begin if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 7b84e1427..95dea5330 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -357,13 +357,8 @@ module lsu .BasePAdrM, .ReadDataBlockSetsM, - // temp - //.SelUncached, .SelFlush, .DCacheMemWriteData, - //.FetchCountFlag, - //.CntEn, - //.CntReset, .DCFetchLine, .DCWriteLine, .BUSACK, @@ -443,9 +438,7 @@ module lsu typedef enum {STATE_BUS_READY, STATE_BUS_FETCH_WDV, - STATE_BUS_FETCH_DONE, - STATE_BUS_EVICT_DIRTY, - STATE_BUS_WRITE_CACHE_BLOCK, + STATE_BUS_WRITE_WDV, STATE_BUS_UNCACHED_WRITE, STATE_BUS_UNCACHED_WRITE_DONE, STATE_BUS_UNCACHED_READ, @@ -495,7 +488,7 @@ module lsu end // D$ Write Line else if(DCWriteLine) begin - BusNextState = STATE_BUS_EVICT_DIRTY; + BusNextState = STATE_BUS_WRITE_WDV; CntReset = 1'b1; BusStall = 1'b1; end @@ -547,7 +540,7 @@ module lsu end end - STATE_BUS_EVICT_DIRTY: begin + STATE_BUS_WRITE_WDV: begin BusStall = 1'b1; PreCntEn = 1'b1; DCtoAHBWriteM = 1'b1; @@ -556,7 +549,7 @@ module lsu BusNextState = STATE_BUS_READY; BUSACK = 1'b1; end else begin - BusNextState = STATE_BUS_EVICT_DIRTY; + BusNextState = STATE_BUS_WRITE_WDV; end end endcase From c2b0e61466665d90494540de17166c024d74538c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 12:11:45 -0600 Subject: [PATCH 06/15] Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw. --- wally-pipelined/src/cache/icache.sv | 2 - wally-pipelined/src/cache/icachefsm.sv | 29 ------------- wally-pipelined/src/ifu/ifu.sv | 2 - wally-pipelined/src/lsu/lsu.sv | 43 +++++++------------ wally-pipelined/src/mmu/hptw.sv | 18 +------- wally-pipelined/src/privileged/privileged.sv | 7 ++- .../src/wally/wallypipelinedhart.sv | 6 +-- 7 files changed, 22 insertions(+), 85 deletions(-) diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index e3e9d6db2..b46a91846 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -48,7 +48,6 @@ module icache output logic ICacheStallF, input logic ITLBMissF, input logic ITLBWriteF, - input logic WalkerInstrPageFaultF, input logic InvalidateICacheM, // The raw (not decompressed) instruction that was requested @@ -289,7 +288,6 @@ module icache .ICacheStallF, .ITLBMissF, .ITLBWriteF, - .WalkerInstrPageFaultF, .ExceptionM, .PendingInterruptM, .InstrAckF, diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index 1d579cd12..867c32c06 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -34,7 +34,6 @@ module icachefsm // inputs from mmu input logic ITLBMissF, input logic ITLBWriteF, - input logic WalkerInstrPageFaultF, input logic ExceptionM, PendingInterruptM, @@ -334,31 +333,8 @@ module icachefsm NextState = STATE_READY; end end -/* -----\/----- EXCLUDED -----\/----- - STATE_TLB_MISS: begin - if (WalkerInstrPageFaultF) begin - NextState = STATE_READY; - ICacheStallF = 1'b0; - end else if (ITLBWriteF) begin - NextState = STATE_TLB_MISS_DONE; - ICacheStallF = 1'b1; - end else begin - NextState = STATE_TLB_MISS; - ICacheStallF = 1'b0; - end - end - STATE_TLB_MISS_DONE: begin - SelAdr = 2'b01; - NextState = STATE_READY; - end - -----/\----- EXCLUDED -----/\----- */ STATE_CPU_BUSY: begin ICacheStallF = 1'b0; -/* -----\/----- EXCLUDED -----\/----- - if (ITLBMissF) begin - NextState = STATE_TLB_MISS; - end else - -----/\----- EXCLUDED -----/\----- */ if(StallF) begin NextState = STATE_CPU_BUSY; SelAdr = 2'b01; @@ -370,11 +346,6 @@ module icachefsm STATE_CPU_BUSY_SPILL: begin ICacheStallF = 1'b0; ICacheReadEn = 1'b1; -/* -----\/----- EXCLUDED -----\/----- - if (ITLBMissF) begin - NextState = STATE_TLB_MISS; - end else - -----/\----- EXCLUDED -----/\----- */ if(StallF) begin NextState = STATE_CPU_BUSY_SPILL; SelAdr = 2'b10; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index a0875e46a..8bc064a9d 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -74,7 +74,6 @@ module ifu ( input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] STATUS_MPP, input logic ITLBWriteF, ITLBFlushF, - input logic WalkerInstrPageFaultF, output logic ITLBMissF, @@ -172,7 +171,6 @@ module ifu ( .PCNextF(PCNextFPhys), .PCPF(PCPFmmu), .PCF, - .WalkerInstrPageFaultF, .InvalidateICacheM); flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 95dea5330..c5df5862d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -83,9 +83,6 @@ module lsu output logic [`XLEN-1:0] PTE, output logic [1:0] PageType, output logic ITLBWriteF, - output logic WalkerInstrPageFaultF, - output logic WalkerLoadPageFaultM, - output logic WalkerStorePageFaultM, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. @@ -120,7 +117,6 @@ module lsu logic CommittedMfromDCache; logic CommittedMfromBus; logic PendingInterruptMtoDCache; - logic WalkerPageFaultM; logic AnyCPUReqM; logic MemAfterIWalkDone; @@ -129,7 +125,6 @@ module lsu typedef enum {STATE_T0_READY, STATE_T0_REPLAY, - STATE_T0_FAULT_REPLAY, STATE_T3_DTLB_MISS, STATE_T4_ITLB_MISS, STATE_T5_ITLB_MISS, @@ -138,8 +133,9 @@ module lsu statetype InterlockCurrState, InterlockNextState; logic InterlockStall; logic SelReplayCPURequest; - logic WalkerInstrPageFaultRaw; logic IgnoreRequest; + + assign AnyCPUReqM = (|MemRWM) | (|AtomicM); @@ -156,18 +152,13 @@ module lsu else InterlockNextState = STATE_T0_READY; STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; else InterlockNextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) InterlockNextState = STATE_T0_READY; - else if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; else InterlockNextState = STATE_T3_DTLB_MISS; - STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) InterlockNextState = STATE_T0_READY; + STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T4_ITLB_MISS; STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; - else if(WalkerInstrPageFaultRaw) InterlockNextState = STATE_T0_FAULT_REPLAY; else InterlockNextState = STATE_T5_ITLB_MISS; - STATE_T0_FAULT_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_FAULT_REPLAY; - else InterlockNextState = STATE_T0_READY; - STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) InterlockNextState = STATE_T0_READY; - else if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; + STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; else InterlockNextState = STATE_T7_DITLB_MISS; default: InterlockNextState = STATE_T0_READY; endcase @@ -178,8 +169,8 @@ module lsu // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (InterlockCurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (InterlockCurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) | - (InterlockCurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (InterlockCurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); + (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); -----/\----- EXCLUDED -----/\----- */ @@ -187,25 +178,23 @@ module lsu InterlockStall = 1'b0; case(InterlockCurrState) STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; - STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1; - STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1; + STATE_T3_DTLB_MISS: InterlockStall = 1'b1; + STATE_T4_ITLB_MISS: InterlockStall = 1'b1; STATE_T5_ITLB_MISS: InterlockStall = 1'b1; - //STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1; - STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1; + STATE_T7_DITLB_MISS: InterlockStall = 1'b1; default: InterlockStall = 1'b0; endcase end // When replaying CPU memory request after PTW select the IEUAdrM for correct address. - assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY) | (InterlockNextState == STATE_T0_FAULT_REPLAY); + assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | - ((InterlockCurrState == STATE_T0_REPLAY | InterlockCurrState == STATE_T0_FAULT_REPLAY) + ((InterlockCurrState == STATE_T0_REPLAY) & (ExceptionM | PendingInterruptM)); - assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | InterlockCurrState == STATE_T0_FAULT_REPLAY; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -217,13 +206,13 @@ module lsu .DTLBMissM(DTLBMissM & ~PendingInterruptM), .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), - .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM, - .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), - .WalkerLoadPageFaultM, .WalkerStorePageFaultM); + .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); + + + assign LSUStall = DCacheStall | InterlockStall | BusStall; - assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; // arbiter between IEU and hptw diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index 81ded4053..63d3456b8 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -45,15 +45,14 @@ module hptw (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic [`PA_BITS-1:0] HPTWAdr, output logic HPTWRead, // HPTW requesting to read memory - output logic [2:0] HPTWSize, // 32 or 64 bit access. - output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults + output logic [2:0] HPTWSize // 32 or 64 bit access. ); typedef enum {L0_ADR, L0_RD, L1_ADR, L1_RD, L2_ADR, L2_RD, L3_ADR, L3_RD, - LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors + LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors generate if (`MEM_VIRTMEM) begin @@ -102,11 +101,6 @@ module hptw assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk; - // Raise faults. DTLBMiss - assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk; - assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBWalk & ~MemWrite; - assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBWalk & MemWrite; - // FSM to track PageType based on the levels of the page table traversed flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType); always_comb @@ -176,7 +170,6 @@ module hptw L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39 else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages else if (ValidNonLeafPTE) NextWalkerState = L2_RD; - //else NextWalkerState = FAULT; else NextWalkerState = LEAF; L2_RD: if (DCacheStall) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; @@ -186,7 +179,6 @@ module hptw L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32 else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages else if (ValidNonLeafPTE) NextWalkerState = L1_RD; - //else NextWalkerState = FAULT; else NextWalkerState = LEAF; L1_RD: if (DCacheStall) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; @@ -195,17 +187,12 @@ module hptw // else NextWalkerState = FAULT; L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages else if (ValidNonLeafPTE) NextWalkerState = L0_RD; - //else NextWalkerState = FAULT; else NextWalkerState = LEAF; L0_RD: if (DCacheStall) NextWalkerState = L0_RD; else NextWalkerState = LEAF; // LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF; // else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; // updates TLB -/* -----\/----- EXCLUDED -----\/----- - FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should. - else NextWalkerState = IDLE; - -----/\----- EXCLUDED -----/\----- */ default: begin // synthesis translate_off $error("Default state in HPTW should be unreachable"); @@ -215,7 +202,6 @@ module hptw endcase end else begin // No Virtual memory supported; tie HPTW outputs to 0 assign HPTWRead = 0; - assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; assign HPTWAdr = 0; assign HPTWSize = 3'b000; end diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index a78db85b3..0afcddb6a 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -50,7 +50,6 @@ module privileged ( input logic DCacheAccess, input logic PrivilegedM, input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM, - input logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM, input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic LoadMisalignedFaultM, input logic StoreMisalignedFaultM, @@ -202,9 +201,9 @@ module privileged ( // lookup or a improperly formatted page table during walking // *** merge these at the lsu level. - assign InstrPageFaultF = ITLBInstrPageFaultF || WalkerInstrPageFaultF; - assign LoadPageFaultM = DTLBLoadPageFaultM || WalkerLoadPageFaultM; - assign StorePageFaultM = DTLBStorePageFaultM || WalkerStorePageFaultM; + assign InstrPageFaultF = ITLBInstrPageFaultF; + assign LoadPageFaultM = DTLBLoadPageFaultM; + assign StorePageFaultM = DTLBStorePageFaultM; // pipeline fault signals flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 0ef69fe73..256c81972 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -75,7 +75,6 @@ module wallypipelinedhart ( logic InstrMisalignedFaultM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM; - logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM; logic [`XLEN-1:0] InstrMisalignedAdrM; @@ -189,7 +188,7 @@ module wallypipelinedhart ( .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ITLBWriteF, .ITLBFlushF, - .WalkerInstrPageFaultF, .ITLBMissF, + .ITLBMissF, // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, @@ -270,8 +269,6 @@ module wallypipelinedhart ( .StoreAccessFaultM, // connects to privilege .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, - .WalkerInstrPageFaultF, .WalkerLoadPageFaultM, - .WalkerStorePageFaultM, .LSUStall); // change to LSUStall @@ -323,7 +320,6 @@ module wallypipelinedhart ( .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM, .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM, - .WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreMisalignedFaultM, .TimerIntM, .ExtIntM, .SwIntM, From b4ab435bff7e0679fb27e391d0bd2776b9841b49 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 13:10:45 -0600 Subject: [PATCH 07/15] Major cleanup of the LSU. --- wally-pipelined/src/cache/dcache.sv | 4 -- wally-pipelined/src/cache/dcachefsm.sv | 2 - wally-pipelined/src/lsu/lrsc.sv | 16 +++---- wally-pipelined/src/lsu/lsu.sv | 59 +++++++++++++------------- 4 files changed, 37 insertions(+), 44 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index fa2b20469..eb692fa81 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -61,8 +61,6 @@ module dcache // inputs from TLB and PMA/P - input logic ExceptionM, - input logic PendingInterruptM, input logic CacheableM, // from ptw input logic IgnoreRequest, @@ -292,8 +290,6 @@ module dcache .BUSACK, .MemRWM, .AtomicM, - .ExceptionM, - .PendingInterruptM, .CPUBusy, .CacheableM, .IgnoreRequest, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index e49c23db7..d45d92e3f 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -33,8 +33,6 @@ module dcachefsm input logic [1:0] AtomicM, input logic FlushDCacheM, // hazard inputs - input logic ExceptionM, - input logic PendingInterruptM, input logic CPUBusy, input logic CacheableM, // hptw inputs diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index a98b7dd5c..d7307702a 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -31,9 +31,9 @@ module lrsc input logic clk, reset, input logic FlushW, CPUBusy, input logic MemReadM, - input logic [1:0] MemRWMtoLRSC, - output logic [1:0] MemRWMtoDCache, - input logic [1:0] AtomicMtoDCache, + input logic [1:0] LsuRWM, + output logic [1:0] DCRWM, + input logic [1:0] LsuAtomicM, input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache output logic SquashSCW ); @@ -45,11 +45,11 @@ module lrsc logic lrM, scM, WriteAdrMatchM; logic SquashSCM; - assign lrM = MemReadM && AtomicMtoDCache[0]; - assign scM = MemRWMtoLRSC[0] && AtomicMtoDCache[0]; - assign WriteAdrMatchM = MemRWMtoLRSC[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign lrM = MemReadM && LsuAtomicM[0]; + assign scM = LsuRWM[0] && LsuAtomicM[0]; + assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; - assign MemRWMtoDCache = SquashSCM ? 2'b00 : MemRWMtoLRSC; + assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc @@ -60,7 +60,7 @@ module lrsc flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); end else begin // Atomic operations not supported assign SquashSCW = 0; - assign MemRWMtoDCache = MemRWMtoLRSC; + assign DCRWM = LsuRWM; end endgenerate endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index c5df5862d..9b0e73518 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -97,10 +97,10 @@ module lsu logic HPTWStall; logic [`PA_BITS-1:0] HPTWAdr; logic HPTWRead; - logic [1:0] MemRWMtoDCache; - logic [1:0] MemRWMtoLRSC; - logic [2:0] Funct3MtoDCache; - logic [1:0] AtomicMtoDCache; + logic [1:0] DCRWM; + logic [1:0] LsuRWM; + logic [2:0] LsuFunct3M; + logic [1:0] LsuAtomicM; logic [`PA_BITS-1:0] MemPAdrNoTranslate; logic [11:0] MemAdrE, MemAdrE_RENAME; logic CPUBusy; @@ -114,7 +114,7 @@ module lsu logic [2:0] HPTWSize; - logic CommittedMfromDCache; + logic DCCommittedM; logic CommittedMfromBus; logic PendingInterruptMtoDCache; @@ -217,21 +217,21 @@ module lsu // arbiter between IEU and hptw // multiplex the outputs to LSU - assign MemRWMtoLRSC = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; + assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; - mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, Funct3MtoDCache); + mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); // this is for the d cache SRAM. // turns out because we cannot pipeline hptw requests we don't need this register //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle - assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM; + assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; assign IEUAdrExtM = {2'b00, IEUAdrM}; assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; assign CPUBusy = SelHPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache | CommittedMfromBus; + assign CommittedM = SelHPTW ? 1'b1 : DCCommittedM | CommittedMfromBus; assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM; @@ -242,7 +242,7 @@ module lsu .PrivilegeModeW, .DisableTranslation(SelHPTW), .PAdr(MemPAdrNoTranslate), .VAdr(IEUAdrM), - .Size(Funct3MtoDCache[1:0]), + .Size(LsuFunct3M[1:0]), .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), @@ -254,15 +254,15 @@ module lsu .TLBPageFault(DTLBPageFaultM), .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), - .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]), + .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? // Move generate from lrsc to outside this module. - assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & InterlockCurrState != STATE_STALLED; - lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, - .SquashSCW, .MemRWMtoDCache); + assign MemReadM = LsuRWM[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & InterlockCurrState != STATE_STALLED; + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, + .SquashSCW, .DCRWM); // *** BUG, this is most likely wrong assign CacheableMtoDCache = SelHPTW ? 1'b1 : CacheableM; @@ -270,8 +270,8 @@ module lsu // Specify which type of page fault is occurring // *** `MEM_VIRTMEM - assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0]; + assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; // Determine if an Unaligned access is taking place // hptw guarantees alignment, only check inputs from IEU. @@ -284,8 +284,8 @@ module lsu endcase // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[1]; - assign StoreMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[0]; + assign LoadMisalignedFaultM = DataMisalignedM & LsuRWM[1]; + assign StoreMisalignedFaultM = DataMisalignedM & LsuRWM[0]; // conditional // 1. ram // controlled by `MEM_DTIM @@ -331,17 +331,16 @@ module lsu logic BUSACK; dcache dcache(.clk, .reset, .CPUBusy, - .MemRWM(MemRWMtoDCache), - .Funct3M(Funct3MtoDCache), + .MemRWM(DCRWM), + .Funct3M(LsuFunct3M), .Funct7M, .FlushDCacheM, - .AtomicM(AtomicMtoDCache), + .AtomicM(LsuAtomicM), .MemAdrE(MemAdrE_RENAME), .MemPAdrM, .VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed. .FinalWriteDataM, .ReadDataWordM, .DCacheStall, - .CommittedM(CommittedMfromDCache), - .DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest, - .PendingInterruptM(PendingInterruptMtoDCache), + .CommittedM(DCCommittedM), + .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableMtoDCache), .BasePAdrM, @@ -366,22 +365,22 @@ module lsu // finally swr subwordread subwordread(.ReadDataWordMuxM, .MemPAdrM(MemPAdrM[2:0]), - .Funct3M(Funct3MtoDCache), + .Funct3M(LsuFunct3M), .ReadDataM); generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3MtoDCache[1:0]), + amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMtoDCache[1], FinalAMOWriteDataM); + mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM); end else assign FinalAMOWriteDataM = WriteDataM; endgenerate subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(MemPAdrM[2:0]), - .HSIZED({Funct3MtoDCache[2], 1'b0, Funct3MtoDCache[1:0]}), + .HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}), .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); @@ -456,14 +455,14 @@ module lsu BusNextState = STATE_BUS_READY; end else // uncache write - if(MemRWMtoDCache[0] & ~CacheableMtoDCache) begin + if(DCRWM[0] & ~CacheableMtoDCache) begin BusNextState = STATE_BUS_UNCACHED_WRITE; CntReset = 1'b1; BusStall = 1'b1; DCtoAHBWriteM = 1'b1; end // uncached read - else if(MemRWMtoDCache[1] & ~CacheableMtoDCache) begin + else if(DCRWM[1] & ~CacheableMtoDCache) begin BusNextState = STATE_BUS_UNCACHED_READ; CntReset = 1'b1; BusStall = 1'b1; From 22bfc80e622cbd7d86328488ff5ea72c17c0a9b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 13:59:07 -0600 Subject: [PATCH 08/15] Additional cleanup of the LSU. --- wally-pipelined/src/lsu/lsu.sv | 62 +++++++++++++++------------------- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 9b0e73518..355b02dc0 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -101,22 +101,20 @@ module lsu logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; - logic [`PA_BITS-1:0] MemPAdrNoTranslate; - logic [11:0] MemAdrE, MemAdrE_RENAME; + logic [`PA_BITS-1:0] LsuPAdrM; + logic [11:0] LsuAdrE, DCAdrE; logic CPUBusy; logic MemReadM; logic DataMisalignedM; logic DCacheStall; logic CacheableM; - logic CacheableMtoDCache; logic SelHPTW; logic [2:0] HPTWSize; logic DCCommittedM; - logic CommittedMfromBus; - logic PendingInterruptMtoDCache; + logic CommittedMfromBus; logic AnyCPUReqM; logic MemAfterIWalkDone; @@ -217,30 +215,30 @@ module lsu // arbiter between IEU and hptw // multiplex the outputs to LSU - assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; - + mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); + mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); + mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); + assign IEUAdrExtM = {2'b00, IEUAdrM}; + mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); + + assign CPUBusy = StallW & ~SelHPTW; + // always block interrupts when using the hardware page table walker. + assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; // this is for the d cache SRAM. // turns out because we cannot pipeline hptw requests we don't need this register //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle - - assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; - assign IEUAdrExtM = {2'b00, IEUAdrM}; - assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; - assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; - assign CPUBusy = SelHPTW ? 1'b0 : StallW; - // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW ? 1'b1 : DCCommittedM | CommittedMfromBus; - - - assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM; - + //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; + //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; + //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; + //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation(SelHPTW), - .PAdr(MemPAdrNoTranslate), + .PAdr(LsuPAdrM), .VAdr(IEUAdrM), .Size(LsuFunct3M[1:0]), .PTE, @@ -260,14 +258,10 @@ module lsu // Move generate from lrsc to outside this module. - assign MemReadM = LsuRWM[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & InterlockCurrState != STATE_STALLED; + assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, .SquashSCW, .DCRWM); - // *** BUG, this is most likely wrong - assign CacheableMtoDCache = SelHPTW ? 1'b1 : CacheableM; - - // Specify which type of page fault is occurring // *** `MEM_VIRTMEM assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; @@ -283,15 +277,15 @@ module lsu 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd endcase - // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedM & LsuRWM[1]; - assign StoreMisalignedFaultM = DataMisalignedM & LsuRWM[0]; + // If the CPU's (not HPTW's) request is a page fault. + assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; + assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; // conditional // 1. ram // controlled by `MEM_DTIM // 2. cache `MEM_DCACHE // 3. wire pass-through - assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0]; + assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE[11:0]; localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); @@ -335,13 +329,13 @@ module lsu .Funct3M(LsuFunct3M), .Funct7M, .FlushDCacheM, .AtomicM(LsuAtomicM), - .MemAdrE(MemAdrE_RENAME), + .MemAdrE(DCAdrE), .MemPAdrM, .VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed. .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .CommittedM(DCCommittedM), .DCacheMiss, .DCacheAccess, .IgnoreRequest, - .CacheableM(CacheableMtoDCache), + .CacheableM(CacheableM), .BasePAdrM, .ReadDataBlockSetsM, @@ -384,7 +378,7 @@ module lsu .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); - assign DCtoAHBWriteData = CacheableMtoDCache | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; + assign DCtoAHBWriteData = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; // Bus Side logic @@ -455,14 +449,14 @@ module lsu BusNextState = STATE_BUS_READY; end else // uncache write - if(DCRWM[0] & ~CacheableMtoDCache) begin + if(DCRWM[0] & ~CacheableM) begin BusNextState = STATE_BUS_UNCACHED_WRITE; CntReset = 1'b1; BusStall = 1'b1; DCtoAHBWriteM = 1'b1; end // uncached read - else if(DCRWM[1] & ~CacheableMtoDCache) begin + else if(DCRWM[1] & ~CacheableM) begin BusNextState = STATE_BUS_UNCACHED_READ; CntReset = 1'b1; BusStall = 1'b1; From b6f4efd458ae8b93ed47b3c2bc7ecc5d70503976 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 14:12:18 -0600 Subject: [PATCH 09/15] More cleanup of dcache. --- wally-pipelined/src/cache/dcache.sv | 18 ++---------------- wally-pipelined/src/lsu/lsu.sv | 11 +++++------ 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index eb692fa81..bff68e451 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -38,7 +38,6 @@ module dcache input logic FlushDCacheM, input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, @@ -63,14 +62,7 @@ module dcache // inputs from TLB and PMA/P input logic CacheableM, // from ptw - input logic IgnoreRequest, - // ahb side -/* -----\/----- EXCLUDED -----\/----- - (* mark_debug = "true" *)output logic AHBRead, - (* mark_debug = "true" *)output logic AHBWrite, - -----/\----- EXCLUDED -----/\----- */ - (* mark_debug = "true" *)input logic AHBAck, // from ahb - (* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM + input logic IgnoreRequest ); localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; @@ -139,9 +131,8 @@ module dcache mux4 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE + .d1(0), // *** REMOVE .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - //.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d3(FlushAdr), .s(SelAdrM), .y(RAdr)); @@ -242,7 +233,6 @@ module dcache .y(SRAMWriteData)); - //assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM; mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), @@ -274,10 +264,6 @@ module dcache assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; - generate - if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : Funct3M; - else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : Funct3M; - endgenerate; //assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 355b02dc0..1bdb37794 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -331,7 +331,6 @@ module lsu .AtomicM(LsuAtomicM), .MemAdrE(DCAdrE), .MemPAdrM, - .VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed. .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .CommittedM(DCCommittedM), .DCacheMiss, .DCacheAccess, .IgnoreRequest, @@ -343,11 +342,7 @@ module lsu .DCacheMemWriteData, .DCFetchLine, .DCWriteLine, - .BUSACK, - - // AHB connection - .AHBAck(1'b0), - .DCtoAHBSizeM + .BUSACK ); @@ -380,6 +375,10 @@ module lsu assign DCtoAHBWriteData = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; + generate + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : LsuFunct3M; + else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : LsuFunct3M; + endgenerate; // Bus Side logic // register the fetch data from the next level of memory. From daac21b3bd96ab105bf2d72f4610ce6f3952bb78 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 14:17:18 -0600 Subject: [PATCH 10/15] Moved generate for lrsc to lsu. --- wally-pipelined/src/lsu/lrsc.sv | 41 ++++++++++++++------------------- wally-pipelined/src/lsu/lsu.sv | 13 ++++++++--- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index d7307702a..1bd2c3ca4 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -38,29 +38,22 @@ module lrsc output logic SquashSCW ); // Handle atomic load reserved / store conditional - generate - if (`A_SUPPORTED) begin // atomic instructions supported - logic [`PA_BITS-1:2] ReservationPAdrW; - logic ReservationValidM, ReservationValidW; - logic lrM, scM, WriteAdrMatchM; - logic SquashSCM; + logic [`PA_BITS-1:2] ReservationPAdrW; + logic ReservationValidM, ReservationValidW; + logic lrM, scM, WriteAdrMatchM; + logic SquashSCM; - assign lrM = MemReadM && LsuAtomicM[0]; - assign scM = LsuRWM[0] && LsuAtomicM[0]; - assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; - assign SquashSCM = scM && ~WriteAdrMatchM; - assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; - always_comb begin // ReservationValidM (next value of valid reservation) - if (lrM) ReservationValidM = 1; // set valid on load reserve - else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc - else ReservationValidM = ReservationValidW; // otherwise don't change valid - end - flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid - flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); - end else begin // Atomic operations not supported - assign SquashSCW = 0; - assign DCRWM = LsuRWM; - end - endgenerate + assign lrM = MemReadM && LsuAtomicM[0]; + assign scM = LsuRWM[0] && LsuAtomicM[0]; + assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign SquashSCM = scM && ~WriteAdrMatchM; + assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; + always_comb begin // ReservationValidM (next value of valid reservation) + if (lrM) ReservationValidM = 1; // set valid on load reserve + else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc + else ReservationValidM = ReservationValidW; // otherwise don't change valid + end + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); + flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 1bdb37794..23ff5d17d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -258,9 +258,16 @@ module lsu // Move generate from lrsc to outside this module. - assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; - lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, - .SquashSCW, .DCRWM); + generate + if (`A_SUPPORTED) begin + assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, + .SquashSCW, .DCRWM); + end else begin + assign SquashSCW = 0; + assign DCRWM = LsuRWM; + end + endgenerate // Specify which type of page fault is occurring // *** `MEM_VIRTMEM From c1789932a499ec539a8573c5b0edfc3004361b1b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 15:00:02 -0600 Subject: [PATCH 11/15] Added generate around virtual memory hardware in LSU. --- wally-pipelined/regression/wave.do | 61 ++---- wally-pipelined/src/cache/dcache.sv | 2 +- wally-pipelined/src/lsu/lsu.sv | 300 +++++++++++++++------------- 3 files changed, 187 insertions(+), 176 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 49413e300..6f09c4f95 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -203,13 +203,13 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit @@ -220,7 +220,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr @@ -328,9 +328,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode @@ -371,19 +376,16 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress @@ -462,29 +464,8 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM -add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE -add wave -noupdate /testbench/dut/hart/ifu/PCSrcE -add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE -add wave -noupdate /testbench/dut/hart/ieu/c/BranchE -add wave -noupdate /testbench/dut/hart/ifu/PCLinkE -add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM -add wave -noupdate /testbench/dut/hart/ifu/PCF -add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR -add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM -add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB -add wave -noupdate /testbench/dut/hart/ifu/temp -add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM -add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM -add wave -noupdate /testbench/dut/hart/lsu/BusCurrState -add wave -noupdate /testbench/dut/hart/lsu/BasePAdrM -add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBPAdrM -add wave -noupdate /testbench/dut/hart/lsu/FetchCountFlag -add wave -noupdate /testbench/dut/hart/lsu/FetchCount -add wave -noupdate /testbench/dut/hart/lsu/DCfromAHBAck -add wave -noupdate /testbench/dut/hart/lsu/BUSACK -add wave -noupdate /testbench/dut/hart/lsu/DCFetchLine TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {2947 ns} 0} +WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {207375 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -500,4 +481,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2791 ns} {3081 ns} +WaveRestoreZoom {207017 ns} {208185 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index bff68e451..0cd5d394b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -131,7 +131,7 @@ module dcache mux4 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(0), // *** REMOVE + .d1(7'b0), // *** REMOVE .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d3(FlushAdr), .s(SelAdrM), diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 23ff5d17d..c098a8c26 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -94,9 +94,7 @@ module lsu logic [`XLEN+1:0] IEUAdrExtM; logic DTLBMissM; logic DTLBWriteM; - logic HPTWStall; - logic [`PA_BITS-1:0] HPTWAdr; - logic HPTWRead; + logic [1:0] DCRWM; logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; @@ -110,151 +108,191 @@ module lsu logic CacheableM; logic SelHPTW; - logic [2:0] HPTWSize; logic DCCommittedM; logic CommittedMfromBus; - logic AnyCPUReqM; - logic MemAfterIWalkDone; logic BusStall; - typedef enum {STATE_T0_READY, - STATE_T0_REPLAY, - STATE_T3_DTLB_MISS, - STATE_T4_ITLB_MISS, - STATE_T5_ITLB_MISS, - STATE_T7_DITLB_MISS} statetype; - - statetype InterlockCurrState, InterlockNextState; logic InterlockStall; - logic SelReplayCPURequest; logic IgnoreRequest; - - assign AnyCPUReqM = (|MemRWM) | (|AtomicM); - - always_ff @(posedge clk) - if (reset) InterlockCurrState <= #1 STATE_T0_READY; - else InterlockCurrState <= #1 InterlockNextState; - - always_comb begin - case(InterlockCurrState) - STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; - else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; - else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; - else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; - else InterlockNextState = STATE_T0_READY; - STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T3_DTLB_MISS; - STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; - else InterlockNextState = STATE_T4_ITLB_MISS; - STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T5_ITLB_MISS; - STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; - else InterlockNextState = STATE_T7_DITLB_MISS; - default: InterlockNextState = STATE_T0_READY; - endcase - end // always_comb - - // signal to CPU it needs to wait on HPTW. - /* -----\/----- EXCLUDED -----\/----- - // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates - // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. - assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | - (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); - - -----/\----- EXCLUDED -----/\----- */ - - always_comb begin - InterlockStall = 1'b0; - case(InterlockCurrState) - STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; - STATE_T3_DTLB_MISS: InterlockStall = 1'b1; - STATE_T4_ITLB_MISS: InterlockStall = 1'b1; - STATE_T5_ITLB_MISS: InterlockStall = 1'b1; - STATE_T7_DITLB_MISS: InterlockStall = 1'b1; - default: InterlockStall = 1'b0; - endcase - end - - - // When replaying CPU memory request after PTW select the IEUAdrM for correct address. - assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); - assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | - (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); - assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | - ((InterlockCurrState == STATE_T0_REPLAY) - & (ExceptionM | PendingInterruptM)); - - - flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); + assign IEUAdrExtM = {2'b00, IEUAdrM}; - // *** add generate to conditionally create hptw, lsuArb, and mmu - // based on `MEM_VIRTMEM - hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, - .ITLBMissF(ITLBMissF & ~PendingInterruptM), - .DTLBMissM(DTLBMissM & ~PendingInterruptM), - .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, - .HPTWReadPTE(ReadDataM), - .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); + generate + if(`MEM_VIRTMEM) begin : MEM_VIRTMEM + logic AnyCPUReqM; + logic [`PA_BITS-1:0] HPTWAdr; + logic HPTWRead; + logic [2:0] HPTWSize; + logic SelReplayCPURequest; + + typedef enum {STATE_T0_READY, + STATE_T0_REPLAY, + STATE_T3_DTLB_MISS, + STATE_T4_ITLB_MISS, + STATE_T5_ITLB_MISS, + STATE_T7_DITLB_MISS} statetype; + + statetype InterlockCurrState, InterlockNextState; + + assign AnyCPUReqM = (|MemRWM) | (|AtomicM); + + always_ff @(posedge clk) + if (reset) InterlockCurrState <= #1 STATE_T0_READY; + else InterlockCurrState <= #1 InterlockNextState; + + always_comb begin + case(InterlockCurrState) + STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; + else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; + else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; + else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; + else InterlockNextState = STATE_T0_READY; + STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T0_READY; + STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T3_DTLB_MISS; + STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; + else InterlockNextState = STATE_T4_ITLB_MISS; + STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T5_ITLB_MISS; + STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; + else InterlockNextState = STATE_T7_DITLB_MISS; + default: InterlockNextState = STATE_T0_READY; + endcase + end // always_comb + + // signal to CPU it needs to wait on HPTW. + /* -----\/----- EXCLUDED -----\/----- + // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates + // everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0. + assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | + (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); + + -----/\----- EXCLUDED -----/\----- */ + + always_comb begin + InterlockStall = 1'b0; + case(InterlockCurrState) + STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1; + STATE_T3_DTLB_MISS: InterlockStall = 1'b1; + STATE_T4_ITLB_MISS: InterlockStall = 1'b1; + STATE_T5_ITLB_MISS: InterlockStall = 1'b1; + STATE_T7_DITLB_MISS: InterlockStall = 1'b1; + default: InterlockStall = 1'b0; + endcase + end + + // When replaying CPU memory request after PTW select the IEUAdrM for correct address. + assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); + assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | + (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); + assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) | + ((InterlockCurrState == STATE_T0_REPLAY) + & (ExceptionM | PendingInterruptM)); + + + // *** add generate to conditionally create hptw, lsuArb, and mmu + // based on `MEM_VIRTMEM + hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, + .ITLBMissF(ITLBMissF & ~PendingInterruptM), + .DTLBMissM(DTLBMissM & ~PendingInterruptM), + .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, + .HPTWReadPTE(ReadDataM), + .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); + + // arbiter between IEU and hptw + + // multiplex the outputs to LSU + mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); + mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); + mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); + mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); + mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); + + assign CPUBusy = StallW & ~SelHPTW; + // always block interrupts when using the hardware page table walker. + assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; + + // this is for the d cache SRAM. + // turns out because we cannot pipeline hptw requests we don't need this register + //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle + + //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; + //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; + //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; + //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; + + + // Specify which type of page fault is occurring + // *** `MEM_VIRTMEM + assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; + + assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; + + end // if (`MEM_VIRTMEM) + else begin + assign InterlockStall = 1'b0; + + assign DCAdrE = LsuAdrE; + assign SelHPTW = 1'b0; + assign IgnoreRequest = 1'b0; + + assign PTE = '0; + assign PageType = '0; + assign DTLBWriteM = 1'b0; + assign ITLBWriteF = 1'b0; + + assign LsuRWM = MemRWM; + assign LsuFunct3M = Funct3M; + assign LsuAtomicM = AtomicM; + assign LsuAdrE = IEUAdrE[11:0]; + assign LsuPAdrM = IEUAdrExtM; + assign CPUBusy = StallW; + assign CommittedM = CommittedMfromBus; + + assign DTLBLoadPageFaultM = 1'b0; + assign DTLBStorePageFaultM = 1'b0; + end + endgenerate + + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) + dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .PrivilegeModeW, .DisableTranslation(SelHPTW), + .PAdr(LsuPAdrM), + .VAdr(IEUAdrM), + .Size(LsuFunct3M[1:0]), + .PTE, + .PageTypeWriteVal(PageType), + .TLBWrite(DTLBWriteM), + .TLBFlush(DTLBFlushM), + .PhysicalAddress(MemPAdrM), + .TLBMiss(DTLBMissM), + .Cacheable(CacheableM), + .Idempotent(), .AtomicAllowed(), + .TLBPageFault(DTLBPageFaultM), + .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, + .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), + .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW + ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? assign LSUStall = DCacheStall | InterlockStall | BusStall; - // arbiter between IEU and hptw - - // multiplex the outputs to LSU - mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); - mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); - mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); - mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); - assign IEUAdrExtM = {2'b00, IEUAdrM}; - mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); - - assign CPUBusy = StallW & ~SelHPTW; - // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; - - // this is for the d cache SRAM. - // turns out because we cannot pipeline hptw requests we don't need this register - //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle - - //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; - //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; - //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; - //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; - - mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(SelHPTW), - .PAdr(LsuPAdrM), - .VAdr(IEUAdrM), - .Size(LsuFunct3M[1:0]), - .PTE, - .PageTypeWriteVal(PageType), - .TLBWrite(DTLBWriteM), - .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), - .TLBMiss(DTLBMissM), - .Cacheable(CacheableM), - .Idempotent(), .AtomicAllowed(), - .TLBPageFault(DTLBPageFaultM), - .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, - .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), - .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW - ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? + // If the CPU's (not HPTW's) request is a page fault. + assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; + assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; // Move generate from lrsc to outside this module. @@ -269,10 +307,6 @@ module lsu end endgenerate - // Specify which type of page fault is occurring - // *** `MEM_VIRTMEM - assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; // Determine if an Unaligned access is taking place // hptw guarantees alignment, only check inputs from IEU. @@ -284,15 +318,11 @@ module lsu 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd endcase - // If the CPU's (not HPTW's) request is a page fault. - assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; - assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; // conditional // 1. ram // controlled by `MEM_DTIM // 2. cache `MEM_DCACHE // 3. wire pass-through - assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE[11:0]; localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); From fe5f016a1661d0368af6f7f16ff3f7b235c1a504 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 15:03:24 -0600 Subject: [PATCH 12/15] Name changes for states in LSU. --- wally-pipelined/src/lsu/lsu.sv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index c098a8c26..2c814aced 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -455,8 +455,8 @@ module lsu assign NextFetchCount = FetchCount + 1'b1; typedef enum {STATE_BUS_READY, - STATE_BUS_FETCH_WDV, - STATE_BUS_WRITE_WDV, + STATE_BUS_FETCH, + STATE_BUS_WRITE, STATE_BUS_UNCACHED_WRITE, STATE_BUS_UNCACHED_WRITE_DONE, STATE_BUS_UNCACHED_READ, @@ -500,13 +500,13 @@ module lsu end // D$ Fetch Line else if(DCFetchLine) begin - BusNextState = STATE_BUS_FETCH_WDV; + BusNextState = STATE_BUS_FETCH; CntReset = 1'b1; BusStall = 1'b1; end // D$ Write Line else if(DCWriteLine) begin - BusNextState = STATE_BUS_WRITE_WDV; + BusNextState = STATE_BUS_WRITE; CntReset = 1'b1; BusStall = 1'b1; end @@ -544,7 +544,7 @@ module lsu SelUncached = 1'b1; end - STATE_BUS_FETCH_WDV: begin + STATE_BUS_FETCH: begin BusStall = 1'b1; PreCntEn = 1'b1; DCtoAHBReadM = 1'b1; @@ -554,11 +554,11 @@ module lsu BusNextState = STATE_BUS_READY; BUSACK = 1'b1; end else begin - BusNextState = STATE_BUS_FETCH_WDV; + BusNextState = STATE_BUS_FETCH; end end - STATE_BUS_WRITE_WDV: begin + STATE_BUS_WRITE: begin BusStall = 1'b1; PreCntEn = 1'b1; DCtoAHBWriteM = 1'b1; @@ -567,7 +567,7 @@ module lsu BusNextState = STATE_BUS_READY; BUSACK = 1'b1; end else begin - BusNextState = STATE_BUS_WRITE_WDV; + BusNextState = STATE_BUS_WRITE; end end endcase From 00ad3a18fb28b09347f7a01df54201a1598abe77 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 15:57:21 -0600 Subject: [PATCH 13/15] Reverted changes to subwordread while keeping the new names of the i/o. --- wally-pipelined/src/lsu/subwordread.sv | 147 ++++++++++++------------- 1 file changed, 69 insertions(+), 78 deletions(-) diff --git a/wally-pipelined/src/lsu/subwordread.sv b/wally-pipelined/src/lsu/subwordread.sv index 1f04c4cb8..eaf2f94a9 100644 --- a/wally-pipelined/src/lsu/subwordread.sv +++ b/wally-pipelined/src/lsu/subwordread.sv @@ -25,99 +25,90 @@ `include "wally-config.vh" -module subwordread ( - input logic [`XLEN-1:0] ReadDataWordMuxM, - input logic [2:0] MemPAdrM, - input logic [2:0] Funct3M, - output logic [`XLEN-1:0] ReadDataM -); - - logic [`XLEN-1:0] offset0, offset1, offset2, offset3; - +module subwordread + ( + input logic [`XLEN-1:0] ReadDataWordMuxM, + input logic [2:0] MemPAdrM, + input logic [2:0] Funct3M, + output logic [`XLEN-1:0] ReadDataM + ); + + logic [7:0] ByteM; + logic [15:0] HalfwordM; // Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[1:0] is the size of the memory access. generate if (`XLEN == 64) begin - logic [`XLEN-1:0] offset4, offset5, offset6, offset7; - + // ByteMe mux always_comb - case(Funct3M[1:0]) - 3: offset0 = ReadDataWordMuxM; //ld - 2: offset0 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[31:0]} : {{32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; //lw(u) - 1: offset0 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[15:0]} : {{48{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u) - 0: offset0 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[7:0]} : {{56{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u) - endcase - - assign offset1 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[15:8]} : {{56{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u) + case(MemPAdrM[2:0]) + 3'b000: ByteM = ReadDataWordMuxM[7:0]; + 3'b001: ByteM = ReadDataWordMuxM[15:8]; + 3'b010: ByteM = ReadDataWordMuxM[23:16]; + 3'b011: ByteM = ReadDataWordMuxM[31:24]; + 3'b100: ByteM = ReadDataWordMuxM[39:32]; + 3'b101: ByteM = ReadDataWordMuxM[47:40]; + 3'b110: ByteM = ReadDataWordMuxM[55:48]; + 3'b111: ByteM = ReadDataWordMuxM[63:56]; + endcase + + // halfword mux + always_comb + case(MemPAdrM[2:1]) + 2'b00: HalfwordM = ReadDataWordMuxM[15:0]; + 2'b01: HalfwordM = ReadDataWordMuxM[31:16]; + 2'b10: HalfwordM = ReadDataWordMuxM[47:32]; + 2'b11: HalfwordM = ReadDataWordMuxM[63:48]; + endcase + + logic [31:0] WordM; always_comb - case(Funct3M[0]) - 1: offset2 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[31:16]} : {{48{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u) - 0: offset2 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[23:16]} : {{56{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u) - endcase - - assign offset3 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[31:24]} : {{56{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u) + case(MemPAdrM[2]) + 1'b0: WordM = ReadDataWordMuxM[31:0]; + 1'b1: WordM = ReadDataWordMuxM[63:32]; + endcase + // sign extension always_comb - case(Funct3M[1:0]) - 3: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//ld(u) // unaligned will cause fault. - 2: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//lw(u) - 1: offset4 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[47:32]} : {{48{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:32]};//lh(u) - 0: offset4 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[39:32]} : {{56{ReadDataWordMuxM[39]}}, ReadDataWordMuxM[39:32]};//lb(u) - endcase - - assign offset5 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[47:40]} : {{56{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:40]};//lb(u) - - always_comb - case(Funct3M[0]) - 1: offset6 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[63:48]} : {{48{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:48]};//lh(u) - 0: offset6 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[55:48]} : {{56{ReadDataWordMuxM[55]}}, ReadDataWordMuxM[55:48]};//lb(u) - endcase - - assign offset7 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[63:56]} : {{56{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:56]};//lb(u) - - // address mux - always_comb - case(MemPAdrM[2:0]) - 0: ReadDataM = offset0; - 1: ReadDataM = offset1; - 2: ReadDataM = offset2; - 3: ReadDataM = offset3; - 4: ReadDataM = offset4; - 5: ReadDataM = offset5; - 6: ReadDataM = offset6; - 7: ReadDataM = offset7; - endcase - + case(Funct3M) + 3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb + 3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw + 3'b011: ReadDataM = ReadDataWordMuxM; // ld + 3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu + 3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu + default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen + endcase end else begin // 32-bit - // byte mux + // byte mux always_comb - case(Funct3M[1:0]) - 3: offset0 = ReadDataWordMuxM; //ld illegal - 2: offset0 = ReadDataWordMuxM[31:0]; //lw - 1: offset0 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[15:0]} : {{16{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u) - 0: offset0 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[7:0]} : {{24{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u) - endcase - - assign offset1 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[15:8]} : {{24{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u) - + case(MemPAdrM[1:0]) + 2'b00: ByteM = ReadDataWordMuxM[7:0]; + 2'b01: ByteM = ReadDataWordMuxM[15:8]; + 2'b10: ByteM = ReadDataWordMuxM[23:16]; + 2'b11: ByteM = ReadDataWordMuxM[31:24]; + endcase + + // halfword mux always_comb - case(Funct3M[0]) - 1: offset2 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[31:16]} : {{16{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u) - 0: offset2 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[23:16]} : {{24{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u) - endcase + case(MemPAdrM[1]) + 1'b0: HalfwordM = ReadDataWordMuxM[15:0]; + 1'b1: HalfwordM = ReadDataWordMuxM[31:16]; + endcase - assign offset3 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[31:24]} : {{24{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u) - - // address mux + // sign extension always_comb - case(MemPAdrM[1:0]) - 0: ReadDataM = offset0; - 1: ReadDataM = offset1; - 2: ReadDataM = offset2; - 3: ReadDataM = offset3; - endcase + case(Funct3M) + 3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb + 3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: ReadDataM = ReadDataWordMuxM; // lw + 3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu + default: ReadDataM = ReadDataWordMuxM; + endcase end endgenerate endmodule From 7044277165c285fd553ef9b94cd3adb6b96722f5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 15:57:36 -0600 Subject: [PATCH 14/15] Changed the bus name between dcache and ebu. --- wally-pipelined/regression/wave.do | 2 +- wally-pipelined/src/ebu/ahblite.sv | 28 +++++----- wally-pipelined/src/lsu/lsu.sv | 52 +++++++++---------- .../src/wally/wallypipelinedhart.sv | 26 +++++----- 4 files changed, 54 insertions(+), 54 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 6f09c4f95..fdda17a8d 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -186,7 +186,7 @@ add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 8ad276ab7..21accf591 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -45,13 +45,13 @@ module ahblite ( output logic [`XLEN-1:0] InstrRData, output logic InstrAckF, // Signals from Data Cache - input logic [`PA_BITS-1:0] DCtoAHBPAdrM, - input logic DCtoAHBReadM, - input logic DCtoAHBWriteM, - input logic [`XLEN-1:0] DCtoAHBWriteData, - output logic [`XLEN-1:0] DCfromAHBReadData, - input logic [1:0] MemSizeM, // *** remove - output logic DCfromAHBAck, + input logic [`PA_BITS-1:0] LsuBusAdr, + input logic LsuBusRead, + input logic LsuBusWrite, + input logic [`XLEN-1:0] LsuBusHWDATA, + output logic [`XLEN-1:0] LsuBusHRDATA, + input logic [2:0] LsuBusSize, + output logic LsuBusAck, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, @@ -98,8 +98,8 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: if (DCtoAHBReadM) NextBusState = MEMREAD; // Memory has priority over instructions - else if (DCtoAHBWriteM)NextBusState = MEMWRITE; + IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions + else if (LsuBusWrite)NextBusState = MEMWRITE; else if (InstrReadF) NextBusState = INSTRREAD; else NextBusState = IDLE; MEMREAD: if (~HREADY) NextBusState = MEMREAD; @@ -116,17 +116,17 @@ module ahblite ( // bus outputs assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); - assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0]; + assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0]; assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (GrantData) ? {1'b0, MemSizeM} : ISize; + assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = NextBusState == MEMWRITE; // delay write data by one cycle for - flop #(`XLEN) wdreg(HCLK, DCtoAHBWriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flop #(`XLEN) wdreg(HCLK, LsuBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); @@ -137,8 +137,8 @@ module ahblite ( assign InstrRData = HRDATA; - assign DCfromAHBReadData = HRDATA; + assign LsuBusHRDATA = HRDATA; assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); - assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); + assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 2c814aced..8544a1377 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -63,13 +63,13 @@ module lsu output logic StoreMisalignedFaultM, StoreAccessFaultM, // connect to ahb -(* mark_debug = "true" *) output logic [`PA_BITS-1:0] DCtoAHBPAdrM, - output logic DCtoAHBReadM, - output logic DCtoAHBWriteM, - input logic DCfromAHBAck, -(* mark_debug = "true" *) input logic [`XLEN-1:0] DCfromAHBReadData, - output logic [`XLEN-1:0] DCtoAHBWriteData, - output logic [2:0] DCtoAHBSizeM, +(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LsuBusAdr, + output logic LsuBusRead, + output logic LsuBusWrite, + input logic LsuBusAck, +(* mark_debug = "true" *) input logic [`XLEN-1:0] LsuBusHRDATA, + output logic [`XLEN-1:0] LsuBusHWDATA, + output logic [2:0] LsuBusSize, // mmu management @@ -410,11 +410,11 @@ module lsu .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); - assign DCtoAHBWriteData = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; + assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; generate - if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : LsuFunct3M; - else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : LsuFunct3M; + if (`XLEN == 32) assign LsuBusSize = CacheableM | SelFlush ? 3'b010 : LsuFunct3M; + else assign LsuBusSize = CacheableM | SelFlush ? 3'b011 : LsuFunct3M; endgenerate; // Bus Side logic @@ -426,8 +426,8 @@ module lsu generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer flopen #(`XLEN) fb(.clk(clk), - .en(DCfromAHBAck & DCtoAHBReadM & (index == FetchCount)), - .d(DCfromAHBReadData), + .en(LsuBusAck & LsuBusRead & (index == FetchCount)), + .d(LsuBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); end endgenerate @@ -438,12 +438,12 @@ module lsu assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; - assign DCtoAHBPAdrM = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; + assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount]; assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & DCfromAHBAck; + assign CntEn = PreCntEn & LsuBusAck; flopenr #(LOGWPL) FetchCountReg(.clk(clk), @@ -473,8 +473,8 @@ module lsu CntReset = 1'b0; BusStall = 1'b0; PreCntEn = 1'b0; - DCtoAHBWriteM = 1'b0; - DCtoAHBReadM = 1'b0; + LsuBusWrite = 1'b0; + LsuBusRead = 1'b0; CommittedMfromBus = 1'b0; BUSACK = 1'b0; SelUncached = 1'b0; @@ -489,14 +489,14 @@ module lsu BusNextState = STATE_BUS_UNCACHED_WRITE; CntReset = 1'b1; BusStall = 1'b1; - DCtoAHBWriteM = 1'b1; + LsuBusWrite = 1'b1; end // uncached read else if(DCRWM[1] & ~CacheableM) begin BusNextState = STATE_BUS_UNCACHED_READ; CntReset = 1'b1; BusStall = 1'b1; - DCtoAHBReadM = 1'b1; + LsuBusRead = 1'b1; end // D$ Fetch Line else if(DCFetchLine) begin @@ -514,9 +514,9 @@ module lsu STATE_BUS_UNCACHED_WRITE : begin BusStall = 1'b1; - DCtoAHBWriteM = 1'b1; + LsuBusWrite = 1'b1; CommittedMfromBus = 1'b1; - if(DCfromAHBAck) begin + if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; end else begin BusNextState = STATE_BUS_UNCACHED_WRITE; @@ -525,9 +525,9 @@ module lsu STATE_BUS_UNCACHED_READ: begin BusStall = 1'b1; - DCtoAHBReadM = 1'b1; + LsuBusRead = 1'b1; CommittedMfromBus = 1'b1; - if(DCfromAHBAck) begin + if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_READ_DONE; end else begin BusNextState = STATE_BUS_UNCACHED_READ; @@ -547,10 +547,10 @@ module lsu STATE_BUS_FETCH: begin BusStall = 1'b1; PreCntEn = 1'b1; - DCtoAHBReadM = 1'b1; + LsuBusRead = 1'b1; CommittedMfromBus = 1'b1; - if (FetchCountFlag & DCfromAHBAck) begin + if (FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; BUSACK = 1'b1; end else begin @@ -561,9 +561,9 @@ module lsu STATE_BUS_WRITE: begin BusStall = 1'b1; PreCntEn = 1'b1; - DCtoAHBWriteM = 1'b1; + LsuBusWrite = 1'b1; CommittedMfromBus = 1'b1; - if(FetchCountFlag & DCfromAHBAck) begin + if(FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; BUSACK = 1'b1; end else begin diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 256c81972..815799caf 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -134,12 +134,12 @@ module wallypipelinedhart ( logic InstrAckF; // AHB LSU interface - logic [`PA_BITS-1:0] DCtoAHBPAdrM; - logic DCtoAHBReadM; - logic DCtoAHBWriteM; - logic DCfromAHBAck; - logic [`XLEN-1:0] DCfromAHBReadData; - logic [`XLEN-1:0] DCtoAHBWriteData; + logic [`PA_BITS-1:0] LsuBusAdr; + logic LsuBusRead; + logic LsuBusWrite; + logic LsuBusAck; + logic [`XLEN-1:0] LsuBusHRDATA; + logic [`XLEN-1:0] LsuBusHWDATA; logic BPPredWrongE; logic BPPredDirWrongM; @@ -148,7 +148,7 @@ module wallypipelinedhart ( logic BPPredClassNonCFIWrongM; logic [4:0] InstrClassM; logic InstrAccessFaultF; - logic [2:0] DCtoAHBSizeM; + logic [2:0] LsuBusSize; logic ExceptionM; logic PendingInterruptM; @@ -246,8 +246,8 @@ module wallypipelinedhart ( .IEUAdrE, .IEUAdrM, .WriteDataM, .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) - .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck, - .DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM, + .LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusAck, + .LsuBusHRDATA, .LsuBusHWDATA, .LsuBusSize, // connect to csr or privilege and stay the same. .PrivilegeModeW, // connects to csr @@ -280,10 +280,10 @@ module wallypipelinedhart ( .InstrPAdrF, // *** rename these to match block diagram .InstrReadF, .InstrRData, .InstrAckF, // Signals from Data Cache - .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCtoAHBWriteData, - .DCfromAHBReadData, - .MemSizeM(DCtoAHBSizeM[1:0]), // *** remove - .DCfromAHBAck, + .LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA, + .LsuBusHRDATA, + .LsuBusSize, + .LsuBusAck, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, From a966764d88577d1fc8964f66b72b829f0253e9cc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 16:14:10 -0600 Subject: [PATCH 15/15] Removed CommittedM as it is redundant with LSUStall. --- wally-pipelined/src/cache/dcache.sv | 2 -- wally-pipelined/src/cache/dcachefsm.sv | 15 --------------- wally-pipelined/src/lsu/lsu.sv | 15 +-------------- wally-pipelined/src/privileged/privileged.sv | 4 ++-- wally-pipelined/src/privileged/trap.sv | 6 +++--- wally-pipelined/src/wally/wallypipelinedhart.sv | 5 ++--- 6 files changed, 8 insertions(+), 39 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0cd5d394b..b1969306c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -42,7 +42,6 @@ module dcache input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, output logic DCacheStall, - output logic CommittedM, output logic DCacheMiss, output logic DCacheAccess, @@ -282,7 +281,6 @@ module dcache .CacheHit, .VictimDirty, .DCacheStall, - .CommittedM, .DCacheMiss, .DCacheAccess, .SelAdrM, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index d45d92e3f..5fa2395bd 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -46,7 +46,6 @@ module dcachefsm // hazard outputs output logic DCacheStall, - output logic CommittedM, // counter outputs output logic DCacheMiss, output logic DCacheAccess, @@ -115,7 +114,6 @@ module dcachefsm ClearDirty = 1'b0; SRAMWordWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0; - CommittedM = 1'b0; SelEvict = 1'b0; LRUWriteEn = 1'b0; SelFlush = 1'b0; @@ -136,7 +134,6 @@ module dcachefsm SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; - CommittedM = 1'b0; // TLB Miss if(IgnoreRequest) begin @@ -146,7 +143,6 @@ module dcachefsm // PTW ready the CPU will stall. // The page table walker asserts it's control 1 cycle // after the TLBs miss. - // CommittedM = 1'b1; ??? *** Not Sure yet. NextState = STATE_READY; end @@ -216,7 +212,6 @@ module dcachefsm STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; @@ -228,7 +223,6 @@ module dcachefsm STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; DCWriteLine = 1'b1; @@ -244,14 +238,12 @@ module dcachefsm SelAdrM = 2'b10; SetValid = 1'b1; ClearDirty = 1'b1; - CommittedM = 1'b1; //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write end STATE_MISS_READ_WORD: begin SelAdrM = 2'b10; DCacheStall = 1'b1; - CommittedM = 1'b1; if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; end else begin @@ -263,7 +255,6 @@ module dcachefsm STATE_MISS_READ_WORD_DELAY: begin //SelAdrM = 2'b10; - CommittedM = 1'b1; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -294,7 +285,6 @@ module dcachefsm SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; @@ -308,7 +298,6 @@ module dcachefsm STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; SelEvict = 1'b1; if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; @@ -319,7 +308,6 @@ module dcachefsm STATE_CPU_BUSY: begin - CommittedM = 1'b1; SelAdrM = 2'b00; if(CPUBusy) begin NextState = STATE_CPU_BUSY; @@ -331,7 +319,6 @@ module dcachefsm end STATE_CPU_BUSY_FINISH_AMO: begin - CommittedM = 1'b1; SelAdrM = 2'b10; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; @@ -349,7 +336,6 @@ module dcachefsm STATE_FLUSH: begin DCacheStall = 1'b1; - CommittedM = 1'b1; SelAdrM = 2'b11; SelFlush = 1'b1; FlushAdrCntEn = 1'b1; @@ -372,7 +358,6 @@ module dcachefsm STATE_FLUSH_WRITE_BACK: begin DCacheStall = 1'b1; SelAdrM = 2'b11; - CommittedM = 1'b1; SelFlush = 1'b1; if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 8544a1377..58394ed47 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -42,7 +42,6 @@ module lsu input logic ExceptionM, input logic PendingInterruptM, input logic FlushDCacheM, - output logic CommittedM, output logic SquashSCW, output logic DCacheMiss, output logic DCacheAccess, @@ -110,9 +109,6 @@ module lsu logic SelHPTW; - logic DCCommittedM; - logic CommittedMfromBus; - logic BusStall; @@ -221,7 +217,6 @@ module lsu assign CPUBusy = StallW & ~SelHPTW; // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; // this is for the d cache SRAM. // turns out because we cannot pipeline hptw requests we don't need this register @@ -259,13 +254,13 @@ module lsu assign LsuAdrE = IEUAdrE[11:0]; assign LsuPAdrM = IEUAdrExtM; assign CPUBusy = StallW; - assign CommittedM = CommittedMfromBus; assign DTLBLoadPageFaultM = 1'b0; assign DTLBStorePageFaultM = 1'b0; end endgenerate + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation(SelHPTW), @@ -369,7 +364,6 @@ module lsu .MemAdrE(DCAdrE), .MemPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, - .CommittedM(DCCommittedM), .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), @@ -475,7 +469,6 @@ module lsu PreCntEn = 1'b0; LsuBusWrite = 1'b0; LsuBusRead = 1'b0; - CommittedMfromBus = 1'b0; BUSACK = 1'b0; SelUncached = 1'b0; @@ -515,7 +508,6 @@ module lsu STATE_BUS_UNCACHED_WRITE : begin BusStall = 1'b1; LsuBusWrite = 1'b1; - CommittedMfromBus = 1'b1; if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; end else begin @@ -526,7 +518,6 @@ module lsu STATE_BUS_UNCACHED_READ: begin BusStall = 1'b1; LsuBusRead = 1'b1; - CommittedMfromBus = 1'b1; if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_READ_DONE; end else begin @@ -535,12 +526,10 @@ module lsu end STATE_BUS_UNCACHED_WRITE_DONE: begin - CommittedMfromBus = 1'b1; BusNextState = STATE_BUS_READY; end STATE_BUS_UNCACHED_READ_DONE: begin - CommittedMfromBus = 1'b1; SelUncached = 1'b1; end @@ -548,7 +537,6 @@ module lsu BusStall = 1'b1; PreCntEn = 1'b1; LsuBusRead = 1'b1; - CommittedMfromBus = 1'b1; if (FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; @@ -562,7 +550,6 @@ module lsu BusStall = 1'b1; PreCntEn = 1'b1; LsuBusWrite = 1'b1; - CommittedMfromBus = 1'b1; if(FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; BUSACK = 1'b1; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 0afcddb6a..9870f5e80 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -39,7 +39,7 @@ module privileged ( output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, LSUStall, input logic FRegWriteM, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, @@ -230,7 +230,7 @@ module privileged ( .PCM, .InstrMisalignedAdrM, .IEUAdrM, .InstrM, - .InstrValidM, .CommittedM, + .InstrValidM, .LSUStall, .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .InterruptM, .ExceptionM, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 02f3f6206..bfeb9de22 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -41,7 +41,7 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, LSUStall, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic ExceptionM, @@ -61,12 +61,12 @@ module trap ( // Determine pending enabled interrupts // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) - // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice + // & with ~LSUStall to make sure MEPC isn't chosen so as to rerun the same instr twice assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); assign PendingInterruptM = (|PendingIntsM) & InstrValidM; - assign InterruptM = PendingInterruptM & ~CommittedM; + assign InterruptM = PendingInterruptM & ~LSUStall; // previously CommittedM. The purpose is to delay an interrupt if the instruction in the memory stage is busy in the LSU. LSUStall directly provides this. //assign ExceptionM = TrapM; assign ExceptionM = Exception1M; // *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 815799caf..95da6c268 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -125,7 +125,6 @@ module wallypipelinedhart ( (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; logic [`XLEN-1:0] ReadDataW; - logic CommittedM; // AHB ifu interface logic [`PA_BITS-1:0] InstrPAdrF; @@ -240,7 +239,7 @@ module wallypipelinedhart ( // CPU interface .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, .ExceptionM, .PendingInterruptM, - .CommittedM, .DCacheMiss, .DCacheAccess, + .DCacheMiss, .DCacheAccess, .SquashSCW, //.DataMisalignedM(DataMisalignedM), .IEUAdrE, .IEUAdrM, .WriteDataM, @@ -314,7 +313,7 @@ module wallypipelinedhart ( .InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM, .ITLBFlushF, .DTLBFlushM, - .InstrValidM, .CommittedM, + .InstrValidM, .LSUStall, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,