From 40c5d3ced72aedab759becd959b1ffa9ba86db0f Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 18 Jul 2021 03:35:38 -0400
Subject: [PATCH] HPTW: Simpliifieid PRegEn
---
wally-pipelined/src/mmu/pagetablewalker.sv | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index 1c4b75252..3c377980b 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -82,7 +82,7 @@ module pagetablewalker
assign CurrentPPN = PTE[`PPN_BITS+9:10];
// State flops
-= flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
+ flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
// Assign PTE descriptors common across all XLEN values
@@ -95,8 +95,8 @@ module pagetablewalker
// Enable and select signals based on states
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
- assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0);
assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ);
+ assign PRegEn = HPTWRead & ~HPTWStall;
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;