Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Updated comments.

Browse Source
This commit is contained in:
Ross Thompson 2023-07-06 15:24:26 -05:00
parent dc50ddd75e
commit 40b2f7ff9c
1 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/uncore/plic_apb.sv
View File

@ -93,13 +93,6 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
assign Din = PWDATA[31:0]; assign Din = PWDATA[31:0];
end end
// *** RT: 05 July 2023: BUG BUG BUG. PLIC_NUM_SRC_LT_32 is undefined after parameterization
// the FPGA does work the following code. For now I'm leaving the `define undefined but this
// means the code is only valid for 33 to 64 interrupt sources. In general this needs to be
// rethought for a more generalized implementation.
//if (P.PLIC_NUM_SRC_LT_32) `define PLIC_NUM_SRC_LT_32
//`define PLIC_NUM_SRC_LT_32
// ================== // ==================
// Register Interface // Register Interface
// ================== // ==================
@ -122,6 +115,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
// verilator lint_off SELRANGE // verilator lint_off SELRANGE
// *** RT: Long term we want to factor out these variable number of registers as a generate loop // *** RT: Long term we want to factor out these variable number of registers as a generate loop
// I think this won't work as a case statement.
24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0];
24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0];
// verilator lint_on SELRANGE // verilator lint_on SELRANGE