diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index c18663afa..9fcfa39c2 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -27,6 +27,15 @@
 
 `include "wally-config.vh"
 
+// `define DEBUG_TRACE 0 // *** move this info down below and remove this line if parametrization works
+// Debug Levels
+// 0: don't check against QEMU
+// 1: print disagreements with QEMU, but only halt on PCW disagreements
+// 2: halt on any disagreement with QEMU except CSRs
+// 3: halt on all disagreements with QEMU
+// 4: print memory accesses whenever they happen
+// 5: print everything
+
 module testbench;
   ///////////////////////////////////////////////////////////////////////////////
   /////////////////////////////////// CONFIG ////////////////////////////////////
@@ -54,6 +63,7 @@ module testbench;
 
 
 
+
   ////////////////////////////////////////////////////////////////////////////////////
   //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS /////////////////////////
   ////////////////////////////////////////////////////////////////////////////////////
@@ -235,6 +245,7 @@ module testbench;
   logic clk, reset_ext; 
   logic reset;
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
+  initial begin $display(DEBUG_TRACE); #1; end // *** remove this once debug trace is parametrized
   always begin clk <= 1; # 5; clk <= 0; # 5; end
   // Wally Interface
   logic [`AHBW-1:0] HRDATAEXT;
@@ -664,7 +675,7 @@ module testbench;
       // turn on waves
       if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
       // end sim
-      if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
+      if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
       fault = 0;
       if (DEBUG_TRACE >= 1) begin
         `checkEQ("PCW",PCW,ExpectedPCW)