From 409ecc53bd6986983ba8fb5badb8d5c45efbc159 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Fri, 3 Nov 2023 04:38:27 -0700
Subject: [PATCH] Fixed regression error of watchdog timeout when PCM is
 optimized out of the IFU

---
 src/ifu/ifu.sv               | 26 ++++++++++++++++----------
 testbench/common/watchdog.sv |  8 +++++---
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 325153ac5..fc3107030 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -114,10 +114,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic [31:0]                 IROMInstrF;                               // Instruction from the IROM
   logic [31:0]                 ICacheInstrF;                             // Instruction from the I$
   logic [31:0]                 InstrRawF;                                // Instruction from the IROM, I$, or bus
-  logic                        CompressedF;                              // The fetched instruction is compressed
-  logic                        CompressedD;                              // The decoded instruction is compressed
-  logic                        CompressedE;                              // The execution instruction is compressed
-  logic                        CompressedM;                              // The execution instruction is compressed
+  logic                        CompressedF, CompressedE;                 // The fetched instruction is compressed
   logic [31:0]                 PostSpillInstrRawF;                       // Fetch instruction after merge two halves of spill
   logic [31:0]                 InstrRawD;                                // Non-decompressed instruction in the Decode stage
   logic                        IllegalIEUInstrD;                         // IEU Instruction (regular or compressed) is not good
@@ -403,17 +400,26 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // PCM is only needed with CSRs or branch prediction
   if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) 
     flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  else assign PCM = 0;
+  else assign PCM = 0; 
 
-  flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
-  flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
-  assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
+  if (P.COMPRESSED_SUPPORTED) begin
+    logic CompressedD;  // instruction is compressed
+    flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
+    flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
+    assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
+  end else begin
+    assign CompressedE = 0;
+    assign PCLinkE = PCE + 'd4;
+  end
 
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  if (P.ZICSR_SUPPORTED) begin
+  if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED) begin
+    logic CompressedM; // instruction is compressed
     flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
     flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
     flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
     mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
-  end else assign InstrOrigM = 0;
+  end else
+    assign InstrOrigM = InstrM;
+
 endmodule
diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv
index 51ed8c30f..1e2b760ca 100644
--- a/testbench/common/watchdog.sv
+++ b/testbench/common/watchdog.sv
@@ -30,11 +30,13 @@ module watchdog #(parameter XLEN, WatchDogTimerThreshold)
    );
   
   // check for hang up.
-  logic [XLEN-1:0]    PCW;
-  flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
-  logic [XLEN-1:0]    OldPCW;
+  logic [XLEN-1:0]      PCM, PCW, OldPCW;
   integer               WatchDogTimerCount;
   logic                 WatchDogTimeOut;
+
+  flopenr #(XLEN) PCMReg(clk, reset, ~dut.core.ifu.StallM, dut.core.ifu.PCE, PCM); // duplicate PCM register because it is not in ifu for all configurations
+  flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, PCM, PCW);
+
   always_ff @(posedge clk) begin
     OldPCW <= PCW;
     if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;