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Merge pull request #381 from harshinisrinath1001/main
Tried to improve coverage of CSRI with priv.S
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commit
409abbf443
@ -64,8 +64,11 @@ trap_handler:
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interrupt: # must be a timer interrupt
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interrupt: # must be a timer interrupt
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLINT
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li t1, 0x02004000 # MTIMECMP in CLIN
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sd t0, 0(t1)
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sd t0, 0(t1)
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csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
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li t0, 32
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csrc sip, t0 # clears stimer interrupt
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j trap_return # clean up and return
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j trap_return # clean up and return
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exception:
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exception:
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@ -59,11 +59,23 @@ sretdone:
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# 1st is when MENVCFG_STCE is cleared
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# 1st is when MENVCFG_STCE is cleared
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li a0, 3
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li a0, 3
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ecall # starts in M-mode
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ecall # starts in M-mode
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li t1, -3
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csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
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li t0, 2
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csrs mstatus, t0 # enables sie
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li t0, 32
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csrs sie, t0 # enables sie.stie
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csrw menvcfg, x0
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csrw menvcfg, x0
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li a0, 1
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li a0, 1
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ecall # enter S-mode
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ecall # enter S-mode
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csrw stimecmp, zero
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csrw stimecmp, zero
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li a0, 3
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li a0, 3
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ecall # in M-mode
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li t0, 32
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csrs sip, t0
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li a0, 1
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ecall # in S-mode and expects stimer interrupt to occur
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li a0, 3
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ecall # return to M-mode
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ecall # return to M-mode
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csrsi mcounteren, 2 # mcounteren_tm = 1
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csrsi mcounteren, 2 # mcounteren_tm = 1
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li a0, 1
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li a0, 1
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