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hptw: Renamed Memstore to MemWrite

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This commit is contained in:
David Harris 2021-07-17 12:01:43 -04:00
parent ddd9110f7b
commit 40989c4e3d
1 changed files with 7 additions and 6 deletions

11
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -76,7 +76,7 @@ module pagetablewalker
logic [`XLEN-1:0] CurrentPTE; logic [`XLEN-1:0] CurrentPTE;
logic [`PA_BITS-1:0] TranslationPAdr; logic [`PA_BITS-1:0] TranslationPAdr;
logic [`PPN_BITS-1:0] CurrentPPN; logic [`PPN_BITS-1:0] CurrentPPN;
logic MemStore; logic MemWrite;
logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid;
logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE; logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE;
logic StartWalk; logic StartWalk;
@ -98,7 +98,7 @@ module pagetablewalker
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign MemStore = MemRWM[0]; assign MemWrite = MemRWM[0];
// Prefer data address translations over instruction address translations // Prefer data address translations over instruction address translations
assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
@ -120,7 +120,7 @@ module pagetablewalker
assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
assign LeafPTE = Executable | Writable | Readable; assign LeafPTE = Executable | Writable | Readable;
assign ValidPTE = Valid && ~(Writable && ~Readable); assign ValidPTE = Valid && ~(Writable && ~Readable);
assign ADPageFault = ~Accessed | (MemStore & ~Dirty); assign ADPageFault = ~Accessed | (MemWrite & ~Dirty);
// Assign specific outputs to general outputs // Assign specific outputs to general outputs
// *** try to eliminate this duplication, but attempts caused MMU to hang // *** try to eliminate this duplication, but attempts caused MMU to hang
@ -132,8 +132,8 @@ module pagetablewalker
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBMissMQ; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBMissMQ;
assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBMissMQ; //*** why do these only get raised on TLB misses? Should they always fault even for ADpagefaults, invalid addresses,etc?? assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBMissMQ; //*** why do these only get raised on TLB misses? Should they always fault even for ADpagefaults, invalid addresses,etc??
assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemStore; assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemWrite;
assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemStore; assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemWrite;
always_comb // determine type of page being walked: always_comb // determine type of page being walked:
case (PreviousWalkerState) case (PreviousWalkerState)
@ -206,6 +206,7 @@ module pagetablewalker
assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
end end
// Walker FSM
always_comb always_comb
case (WalkerState) case (WalkerState)
IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState; IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState;