CoreMark testing

tests/riscv-coremark/riscv64-baremetal/core_portme.c

@@ -195,8 +195,11 @@ void stop_time(void) {
 */
 CORE_TICKS get_time(void) {
 	CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
-	//ee_printf("    Elapsed MTIME: %u\n", elapsed);
+	unsigned long instructions = minstretDiff();
-	//ee_printf("    Elapsed MINSTRET: %lu\n", minstretDiff());
+	double CPI = elapsed / instructions;
+	ee_printf("    Elapsed MTIME: %u\n", elapsed);
+	ee_printf("    Elapsed MINSTRET: %lu\n", instructions);
+	ee_printf("    CPI: %lf", CPI);
 	return elapsed;
 }
 /* Function: time_in_secs

wally-pipelined/regression/sim-wally-batch

@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64g arch64d
+do wally-pipelined-batch.do rv32g arch32f
 !

wally-pipelined/regression/wally-coremark_bare.do

@@ -1,118 +0,0 @@
-# wally-coremark.do 
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# Use this wally-coremark.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-coremark.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-coremark.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# default to config/coremark, but allow this to be overridden at the command line.  For example:
-vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt +acc work.testbench -o workopt 
-vsim workopt
-
-mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
-
-view wave
-
--- display input and output signals as hexidecimal values
-# Diplays All Signals recursively
-add wave /testbench/clk
-add wave /testbench/reset
-add wave -divider
-#add wave /testbench/dut/hart/ebu/IReadF
-#add wave /testbench/dut/hart/DataStall
-#add wave /testbench/dut/hart/InstrStall
-#add wave /testbench/dut/hart/StallF
-#add wave /testbench/dut/hart/StallD
-#add wave /testbench/dut/hart/FlushD
-#add wave /testbench/dut/hart/FlushE
-#add wave /testbench/dut/hart/FlushM
-#add wave /testbench/dut/hart/FlushW
-
-add wave -divider Fetch
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
-add wave /testbench/InstrFName
-add wave -divider Decode
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
-add wave /testbench/InstrDName
-add wave -divider Execute
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
-add wave /testbench/InstrEName
-add wave -divider Memory
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
-add wave /testbench/InstrMName
-add wave -divider Write
-add wave -hex /testbench/PCW
-add wave -hex /testbench/InstrW
-add wave /testbench/InstrWName
-#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
-add wave -divider Regfile_signals
-#add wave /testbench/dut/uncore/dtim/memwrite
-#add wave -hex /testbench/dut/uncore/HADDR
-#add wave -hex /testbench/dut/uncore/HWDATA
-#add wave -divider
-#add wave -hex /testbench/PCW
-#add wave /testbench/InstrWName
-#add wave /testbench/dut/hart/ieu/dp/RegWriteW
-#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-#add wave -hex /testbench/dut/hart/ieu/dp/RdW
-add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
-add wave -divider Regfile_itself
-add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
-add wave -divider RAM
-#add wave -hex -r /testbench/dut/uncore/dtim/RAM
-add wave -divider Misc
-add wave -divider
-#add wave -hex -r /testbench/*
-
--- Set Wave Output Items 
-TreeUpdate [SetDefaultTree]
-WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 120
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
-
--- Run the Simulation 
-#run 7402000
-#run 12750
-run -all
-#run 21400
-#quit

wally-pipelined/testbench/testbench-coremark_bare.sv

@@ -26,7 +26,7 @@
 `include "wally-config.vh"
 module testbench();
   logic        clk;
-  logic        reset;
+  logic        reset, reset_ext;
   int test, i, errors, totalerrors;
   logic [31:0] sig32[10000:0];
   logic [`XLEN-1:0] signature[10000:0];
@@ -48,7 +48,7 @@ module testbench();
   
   // pick tests based on modes supported
   initial 
-  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
+  tests = {"../../tests/imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
@@ -64,12 +64,18 @@ module testbench();
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
 
   // Track names of instructions
+    instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
+                dut.hart.ifu.icache.FinalInstrRawF,
+                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
+                dut.hart.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+/*
   instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
                 dut.hart.ifu.icache.controller.FinalInstrRawF,
                 dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
                 dut.hart.ifu.InstrM, InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
+*/
   logic [`XLEN-1:0] PCW;
   flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
   
@@ -86,7 +92,7 @@ module testbench();
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
         //dut.uncore.dtim.RAM[268437713]=64'b1;
-    reset = 1; # 22; reset = 0;
+    reset_ext = 1; # 22; reset_ext = 0;
     end
   // generate clock to sequence tests
   always
@@ -103,8 +109,11 @@ module testbench();
     end
 
   initial begin
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
+//    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
-    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
+//    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
+    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+	  $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+
   end
    
 endmodule

wally-pipelined/testbench/tests.vh

@@ -895,12 +895,12 @@ string imperas32f[] = '{
     // "rv32i_m/F/flt_b1-01", "6220",
     // "rv32i_m/F/flt_b19-01", "8ee0",
     "rv32i_m/F/flw-align-01", "2010",
-//    "rv32i_m/F/fmadd_b1-01", "96860",
+    "rv32i_m/F/fmadd_b1-01", "96860",
     "rv32i_m/F/fmadd_b14-01", "23d0",
 //--passes but is timeconsuming    "rv32i_m/F/fmadd_b15-01", "19bb30",
     "rv32i_m/F/fmadd_b16-01", "39d0",
     "rv32i_m/F/fmadd_b17-01", "39d0",
-//    "rv32i_m/F/fmadd_b18-01", "4d10",
+    "rv32i_m/F/fmadd_b18-01", "4d10",
     "rv32i_m/F/fmadd_b2-01", "4d60",
     "rv32i_m/F/fmadd_b3-01", "d4f0",
     "rv32i_m/F/fmadd_b4-01", "3700",