diff --git a/benchmarks/riscv-coremark/Makefile b/benchmarks/riscv-coremark/Makefile
index a5b472394..1247d3d75 100644
--- a/benchmarks/riscv-coremark/Makefile
+++ b/benchmarks/riscv-coremark/Makefile
@@ -14,10 +14,11 @@ work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
 
 work/coremark.bare.riscv: $(sources)
 #	make -C $(cmbase) PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64g"
-	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im"
-	mv $(cmbase)/coremark.bare.riscv work
+	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv XCFLAGS="-march=rv64imd"
+	mkdir -p work/
+	mv $(cmbase)/coremark.bare.riscv work/
 
 .PHONY: clean
 
 clean:
-	rm -f work/*
\ No newline at end of file
+	rm -f work/*
diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 828c2b7cf..a0591d6ad 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -34,7 +34,7 @@ configs = [
 ]
 def getBuildrootTC(short):
     INSTR_LIMIT = 100000 # multiple of 100000
-    MAX_EXPECTED = 182000000
+    MAX_EXPECTED = 246000000
     if short:
         BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
index 37b26f8b3..b403016aa 100644
--- a/wally-pipelined/regression/wally-coremark.do
+++ b/wally-pipelined/regression/wally-coremark.do
@@ -35,7 +35,7 @@ vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testb
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
-mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
+mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/dtim/RAM
 
 view wave
 
diff --git a/wally-pipelined/src/fpu/fcmp.sv b/wally-pipelined/src/fpu/fcmp.sv
index b47e6eab9..a60cc8f64 100755
--- a/wally-pipelined/src/fpu/fcmp.sv
+++ b/wally-pipelined/src/fpu/fcmp.sv
@@ -76,7 +76,12 @@ module fcmp (
 
    // Determine final values based on output of magnitude comparison, 
    // sign bits, and special case testing. 
-   exception_cmp_2 exc2 (.invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ), .ANaN(XNaNE), .BNaN(YNaNE), .Azero(XZeroE), .Bzero(YZeroE), .FOpCtrlE(FOpCtrlE), .A(op1), .B(op2), .FSrcXE, .FSrcYE, .*);
+   exception_cmp_2 exc2 (
+      .invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ), 
+      .ANaN(XNaNE), .BNaN(YNaNE), .Azero(XZeroE), .Bzero(YZeroE), 
+      .FOpCtrlE, .A(op1), .B(op2), .FSrcXE, .FSrcYE, 
+      .FmtE, .CmpResE
+      );
 
 endmodule // fpcomp
 
diff --git a/wally-pipelined/src/sdc/counter.sv b/wally-pipelined/src/sdc/SDCcounter.sv
similarity index 100%
rename from wally-pipelined/src/sdc/counter.sv
rename to wally-pipelined/src/sdc/SDCcounter.sv
diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index 59beebb6d..31d8fec5f 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
+module dtim #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
   input  logic             HSELTim,
   input  logic [31:0]      HADDR,
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index 50941c325..97057b23b 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -103,7 +103,7 @@ module uncore (
     end
 
     if (`BOOTTIM_SUPPORTED) begin : bootdtim
-      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE), .PRELOAD("blink-led.mem"))
+      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE))
       bootdtim(
         .HCLK, .HRESETn, 
         .HSELTim(HSELBootTim), .HADDR,
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index ebf6e29a3..06ca47b07 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -54,8 +54,13 @@ module testbench();
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
   logic SDCCLK;
-  tri1 SDCCmd;
-  tri1 [3:0] SDCDat;
+  logic      SDCCmdIn;
+  logic      SDCCmdOut;
+  logic      SDCCmdOE;
+  logic [3:0] SDCDatIn;
+
+  logic             HREADY;
+  logic 	    HSELEXT;
 
   assign SDCmd = 1'bz;
   assign SDCDat = 4'bz;
@@ -95,7 +100,7 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.uncore.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
       //for(j=268437955; j < 268566528; j = j+1)
         //dut.uncore.dtim.RAM[j] = 64'b0;
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";