From bc6e7766099b34cff858363f8baaa93d391ba8b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 10:58:02 -0600 Subject: [PATCH 1/7] Converted mux4 to mux3 in dcache. --- wally-pipelined/src/cache/dcache.sv | 7 ++--- wally-pipelined/src/cache/dcachefsm.sv | 42 +++++++++++++------------- wally-pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 25 insertions(+), 26 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ccfc7fa3a..1a41e7aa5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -128,11 +128,10 @@ module dcache // Read Path CPU (IEU) side - mux4 #(INDEXLEN) + mux3 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(7'b0), // *** REMOVE - .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d3(FlushAdr), + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d2(FlushAdr), .s(SelAdrM), .y(RAdr)); diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 35df55281..09594ce4d 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -150,19 +150,19 @@ module dcachefsm else if(FlushDCacheM) begin NextState = STATE_FLUSH; DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; FlushAdrCntRst = 1'b1; FlushWayCntRst = 1'b1; end // amo hit else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b0; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin SRAMWordWriteEnableM = 1'b1; @@ -178,7 +178,7 @@ module dcachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -186,7 +186,7 @@ module dcachefsm end // write hit valid cached else if (MemRWM[0] & CacheableM & CacheHit) begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; @@ -194,7 +194,7 @@ module dcachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -211,7 +211,7 @@ module dcachefsm STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; @@ -222,7 +222,7 @@ module dcachefsm STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; DCWriteLine = 1'b1; @@ -235,14 +235,14 @@ module dcachefsm SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; NextState = STATE_MISS_READ_WORD; - SelAdrM = 2'b10; + SelAdrM = 2'b01; SetValid = 1'b1; ClearDirty = 1'b1; //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write end STATE_MISS_READ_WORD: begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b1; if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; @@ -254,12 +254,12 @@ module dcachefsm end STATE_MISS_READ_WORD_DELAY: begin - //SelAdrM = 2'b10; + //SelAdrM = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; if(&MemRWM & AtomicM[1]) begin // amo write - SelAdrM = 2'b10; + SelAdrM = 2'b01; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; end @@ -273,7 +273,7 @@ module dcachefsm LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -284,11 +284,11 @@ module dcachefsm STATE_MISS_WRITE_WORD: begin SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -297,7 +297,7 @@ module dcachefsm STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; SelEvict = 1'b1; if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; @@ -311,7 +311,7 @@ module dcachefsm SelAdrM = 2'b00; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -319,7 +319,7 @@ module dcachefsm end STATE_CPU_BUSY_FINISH_AMO: begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -336,7 +336,7 @@ module dcachefsm STATE_FLUSH: begin DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; SelFlush = 1'b1; FlushAdrCntEn = 1'b1; FlushWayCntEn = 1'b1; @@ -357,7 +357,7 @@ module dcachefsm STATE_FLUSH_WRITE_BACK: begin DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; SelFlush = 1'b1; if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; @@ -371,7 +371,7 @@ module dcachefsm ClearDirty = 1'b1; VDWriteEnable = 1'b1; SelFlush = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; if(FlushAdrFlag) begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index d325f1ad5..248793141 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -488,7 +488,7 @@ module lsu STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_READY; STATE_BUS_FETCH: if (WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_FETCH; STATE_BUS_WRITE: if(WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; From 995cfb1cf345c7b42dfc9ecb08c68066bb5e6129 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 11:21:44 -0600 Subject: [PATCH 2/7] Cleaned up some names in dcache and lsu. --- wally-pipelined/src/cache/dcache.sv | 262 +++++++++++-------------- wally-pipelined/src/cache/dcachefsm.sv | 26 +-- wally-pipelined/src/lsu/lrsc.sv | 4 +- wally-pipelined/src/lsu/lsu.sv | 54 ++--- 4 files changed, 152 insertions(+), 194 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 1a41e7aa5..6d13a1a17 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -38,17 +38,17 @@ module dcache input logic FlushDCacheM, input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - + input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, output logic DCacheStall, output logic DCacheMiss, output logic DCacheAccess, - output logic DCCommittedM, - output logic DCWriteLine, - output logic DCFetchLine, - input logic BUSACK, - + output logic DCacheCommittedM, + output logic DCacheWriteLine, + output logic DCacheFetchLine, + input logic DCacheBusAck, + output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], @@ -64,119 +64,105 @@ module dcache input logic IgnoreRequest ); - localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; - localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; - localparam integer NUMWAYS = `DCACHE_NUMWAYS; + localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; + localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; + localparam integer NUMWAYS = `DCACHE_NUMWAYS; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; - localparam integer LOGWPL = $clog2(WORDSPERLINE); - localparam integer LOGXLENBYTES = $clog2(`XLEN/8); + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer LOGWPL = $clog2(WORDSPERLINE); + localparam integer LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer FlushAdrThreshold = NUMLINES - 1; + localparam integer FlushAdrThreshold = NUMLINES - 1; - logic [1:0] SelAdrM; - logic [INDEXLEN-1:0] RAdr; - logic [INDEXLEN-1:0] WAdr; - logic [BLOCKLEN-1:0] SRAMWriteData; - logic SetValid, ClearValid; - logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] WayHit; - logic CacheHit; - logic [BLOCKLEN-1:0] ReadDataBlockM; - logic [`XLEN-1:0] ReadDataWordMuxM; - logic [WORDSPERLINE-1:0] SRAMWordEnable; + logic [1:0] SelAdrM; + logic [INDEXLEN-1:0] RAdr; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic SetValid, ClearValid; + logic SetDirty, ClearDirty; + logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] WayHit; + logic CacheHit; + logic [BLOCKLEN-1:0] ReadDataBlockM; + logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SRAMWordWriteEnableM; - logic SRAMBlockWriteEnableM; - logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; - //logic SRAMWriteEnable; - logic [NUMWAYS-1:0] SRAMWayWriteEnable; + logic SRAMWordWriteEnableM; + logic SRAMBlockWriteEnableM; + logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; + logic [NUMWAYS-1:0] SRAMWayWriteEnable; - logic [NUMWAYS-1:0] VictimWay; - logic [NUMWAYS-1:0] VictimDirtyWay; - logic VictimDirty; + logic [NUMWAYS-1:0] VictimWay; + logic [NUMWAYS-1:0] VictimDirtyWay; + logic VictimDirty; - logic [2**LOGWPL-1:0] MemPAdrDecodedW; + logic [2**LOGWPL-1:0] MemPAdrDecodedW; - logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; - logic [TAGLEN-1:0] VictimTag; + logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; + logic [TAGLEN-1:0] VictimTag; - logic [INDEXLEN-1:0] FlushAdr; - logic [INDEXLEN-1:0] FlushAdrP1; - logic FlushAdrCntEn; - logic FlushAdrCntRst; - logic FlushAdrFlag; + logic [INDEXLEN-1:0] FlushAdr; + logic [INDEXLEN-1:0] FlushAdrP1; + logic FlushAdrCntEn; + logic FlushAdrCntRst; + logic FlushAdrFlag; - logic [NUMWAYS-1:0] FlushWay; - logic [NUMWAYS-1:0] NextFlushWay; - logic FlushWayCntEn; - logic FlushWayCntRst; - - logic VDWriteEnable; - - logic SelEvict; + logic [NUMWAYS-1:0] FlushWay; + logic [NUMWAYS-1:0] NextFlushWay; + logic FlushWayCntEn; + logic FlushWayCntRst; - logic LRUWriteEn; - - logic [NUMWAYS-1:0] VDWriteEnableWay; + logic VDWriteEnable; + logic SelEvict; + logic LRUWriteEn; + logic [NUMWAYS-1:0] VDWriteEnableWay; // Read Path CPU (IEU) side mux3 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(FlushAdr), - .s(SelAdrM), - .y(RAdr)); - - mux2 #(INDEXLEN) - WAdrSelMux(.d0(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(FlushAdr), - .s(&SelAdrM), - .y(WAdr)); - - + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d2(FlushAdr), + .s(SelAdrM), + .y(RAdr)); cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) MemWay[NUMWAYS-1:0](.clk, - .reset, - .RAdr, - .WAdr, - .PAdr(MemPAdrM), - .WriteEnable(SRAMWayWriteEnable), - .VDWriteEnable(VDWriteEnableWay), - .WriteWordEnable(SRAMWordEnable), - .TagWriteEnable(SRAMBlockWayWriteEnableM), - .WriteData(SRAMWriteData), - .SetValid, - .ClearValid, - .SetDirty, - .ClearDirty, - .SelEvict, - .VictimWay, - .FlushWay, - .SelFlush, - .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), - .WayHit, - .VictimDirtyWay, - .VictimTagWay, - .InvalidateAll(1'b0)); + .reset, + .RAdr, + .WAdr(RAdr), // *** Reduce after addressing in icache also + .PAdr(MemPAdrM), + .WriteEnable(SRAMWayWriteEnable), + .VDWriteEnable(VDWriteEnableWay), + .WriteWordEnable(SRAMWordEnable), + .TagWriteEnable(SRAMBlockWayWriteEnableM), + .WriteData(SRAMWriteData), + .SetValid, + .ClearValid, + .SetDirty, + .ClearDirty, + .SelEvict, + .VictimWay, + .FlushWay, + .SelFlush, + .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), + .WayHit, + .VictimDirtyWay, + .VictimTagWay, + .InvalidateAll(1'b0)); generate if(NUMWAYS > 1) begin cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(.clk, .reset, - .WayHit, - .VictimWay, - .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .RAdr, - .LRUWriteEn); + .WayHit, + .VictimWay, + .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .RAdr, + .LRUWriteEn); end else begin assign VictimWay = 1'b1; // one hot. end @@ -207,54 +193,53 @@ module dcache assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - // Write Path CPU (IEU) side onehotdecoder #(LOGWPL) adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), - .decoded(MemPAdrDecodedW)); + .decoded(MemPAdrDecodedW)); assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0; mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), - .d1(SRAMBlockWayWriteEnableM), - .s(SRAMBlockWriteEnableM), - .y(SRAMWayWriteEnable)); + .d1(SRAMBlockWayWriteEnableM), + .s(SRAMBlockWriteEnableM), + .y(SRAMWayWriteEnable)); mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), - .d1(DCacheMemWriteData), - .s(SRAMBlockWriteEnableM), - .y(SRAMWriteData)); + .d1(DCacheMemWriteData), + .s(SRAMBlockWriteEnableM), + .y(SRAMWriteData)); mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(DCacheBusAdr)); + .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), + .s({SelFlush, SelEvict}), + .y(DCacheBusAdr)); // flush address and way generation. flopenr #(INDEXLEN) FlushAdrReg(.clk, - .reset(reset | FlushAdrCntRst), - .en(FlushAdrCntEn & FlushWay[NUMWAYS-1]), - .d(FlushAdrP1), - .q(FlushAdr)); + .reset(reset | FlushAdrCntRst), + .en(FlushAdrCntEn & FlushWay[NUMWAYS-1]), + .d(FlushAdrP1), + .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; flopenl #(NUMWAYS) FlushWayReg(.clk, - .load(reset | FlushWayCntRst), - .en(FlushWayCntEn), - .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), - .q(FlushWay)); + .load(reset | FlushWayCntRst), + .en(FlushWayCntEn), + .val({{NUMWAYS-1{1'b0}}, 1'b1}), + .d(NextFlushWay), + .q(FlushWay)); assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}}; @@ -262,44 +247,17 @@ module dcache assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; - - //assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; - // controller - dcachefsm dcachefsm(.clk, - .reset, - .DCFetchLine, - .DCWriteLine, - .BUSACK, - .MemRWM, - .AtomicM, - .CPUBusy, - .CacheableM, - .IgnoreRequest, - .CacheHit, - .VictimDirty, - .DCacheStall, - .DCCommittedM, - .DCacheMiss, - .DCacheAccess, - .SelAdrM, - .SetValid, - .ClearValid, - .SetDirty, - .ClearDirty, - .SRAMWordWriteEnableM, - .SRAMBlockWriteEnableM, - .SelEvict, - .SelFlush, - .FlushAdrCntEn, - .FlushWayCntEn, - .FlushAdrCntRst, - .FlushWayCntRst, - .FlushAdrFlag, - .FlushDCacheM, - .VDWriteEnable, - .LRUWriteEn); + dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, + .MemRWM, .AtomicM, .CPUBusy, .CacheableM, .IgnoreRequest, + .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM, + .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid, + .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, + .SRAMBlockWriteEnableM, .SelEvict, .SelFlush, + .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, + .FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM, + .VDWriteEnable, .LRUWriteEn); endmodule // dcache diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 09594ce4d..418a1ad20 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -38,7 +38,7 @@ module dcachefsm // hptw inputs input logic IgnoreRequest, // Bus inputs - input logic BUSACK, + input logic DCacheBusAck, // dcache internals input logic CacheHit, input logic VictimDirty, @@ -50,9 +50,9 @@ module dcachefsm output logic DCacheMiss, output logic DCacheAccess, // Bus outputs - output logic DCCommittedM, - output logic DCWriteLine, - output logic DCFetchLine, + output logic DCacheCommittedM, + output logic DCacheWriteLine, + output logic DCacheFetchLine, // dcache internals output logic [1:0] SelAdrM, @@ -123,8 +123,8 @@ module dcachefsm FlushWayCntRst = 1'b0; VDWriteEnable = 1'b0; NextState = STATE_READY; - DCFetchLine = 1'b0; - DCWriteLine = 1'b0; + DCacheFetchLine = 1'b0; + DCacheWriteLine = 1'b0; case (CurrState) STATE_READY: begin @@ -204,7 +204,7 @@ module dcachefsm else if((|MemRWM) & CacheableM & ~CacheHit) begin NextState = STATE_MISS_FETCH_WDV; DCacheStall = 1'b1; - DCFetchLine = 1'b1; + DCacheFetchLine = 1'b1; end else NextState = STATE_READY; end @@ -213,7 +213,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b01; - if (BUSACK) begin + if (DCacheBusAck) begin NextState = STATE_MISS_FETCH_DONE; end else begin NextState = STATE_MISS_FETCH_WDV; @@ -225,7 +225,7 @@ module dcachefsm SelAdrM = 2'b01; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; - DCWriteLine = 1'b1; + DCacheWriteLine = 1'b1; end else begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end @@ -299,7 +299,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b01; SelEvict = 1'b1; - if(BUSACK) begin + if(DCacheBusAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin NextState = STATE_MISS_EVICT_DIRTY; @@ -344,7 +344,7 @@ module dcachefsm NextState = STATE_FLUSH_WRITE_BACK; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; - DCWriteLine = 1'b1; + DCacheWriteLine = 1'b1; end else if (FlushAdrFlag) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -359,7 +359,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b10; SelFlush = 1'b1; - if(BUSACK) begin + if(DCacheBusAck) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin NextState = STATE_FLUSH_WRITE_BACK; @@ -391,7 +391,7 @@ module dcachefsm endcase end - assign DCCommittedM = CurrState != STATE_READY; + assign DCacheCommittedM = CurrState != STATE_READY; endmodule // dcachefsm diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index 1bd2c3ca4..77e59cd37 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -32,7 +32,7 @@ module lrsc input logic FlushW, CPUBusy, input logic MemReadM, input logic [1:0] LsuRWM, - output logic [1:0] DCRWM, + output logic [1:0] DCacheRWM, input logic [1:0] LsuAtomicM, input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache output logic SquashSCW @@ -47,7 +47,7 @@ module lrsc assign scM = LsuRWM[0] && LsuAtomicM[0]; assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; - assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; + assign DCacheRWM = SquashSCM ? 2'b00 : LsuRWM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 248793141..da35471f1 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -95,12 +95,12 @@ module lsu logic DTLBMissM; logic DTLBWriteM; - logic [1:0] DCRWM; + logic [1:0] DCacheRWM; logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; - logic [11:0] LsuAdrE, DCAdrE; + logic [11:0] LsuAdrE, DCacheAdrE; logic CPUBusy; logic MemReadM; logic DataMisalignedM; @@ -115,7 +115,7 @@ module lsu logic InterlockStall; logic IgnoreRequest; - logic BusCommittedM, DCCommittedM; + logic BusCommittedM, DCacheCommittedM; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -236,13 +236,13 @@ module lsu assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; - assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; + assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; end // if (`MEM_VIRTMEM) else begin assign InterlockStall = 1'b0; - assign DCAdrE = LsuAdrE; + assign DCacheAdrE = LsuAdrE; assign SelHPTW = 1'b0; assign IgnoreRequest = 1'b0; @@ -263,7 +263,7 @@ module lsu end endgenerate - assign CommittedM = SelHPTW | DCCommittedM | BusCommittedM; + assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, @@ -299,10 +299,10 @@ module lsu if (`A_SUPPORTED) begin assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, - .SquashSCW, .DCRWM); + .SquashSCW, .DCacheRWM); end else begin assign SquashSCW = 0; - assign DCRWM = LsuRWM; + assign DCacheRWM = LsuRWM; end endgenerate @@ -355,9 +355,9 @@ module lsu - logic DCWriteLine; - logic DCFetchLine; - logic BUSACK; + logic DCacheWriteLine; + logic DCacheFetchLine; + logic DCacheBusAck; logic UnCachedLsuBusRead; logic UnCachedLsuBusWrite; @@ -365,23 +365,23 @@ module lsu dcache dcache(.clk, .reset, .CPUBusy, - .MemRWM(DCRWM), + .MemRWM(DCacheRWM), .Funct3M(LsuFunct3M), .Funct7M, .FlushDCacheM, .AtomicM(LsuAtomicM), - .MemAdrE(DCAdrE), + .MemAdrE(DCacheAdrE), .MemPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), - .DCCommittedM, + .DCacheCommittedM, .DCacheBusAdr, .ReadDataBlockSetsM, .SelFlush, .DCacheMemWriteData, - .DCFetchLine, - .DCWriteLine, - .BUSACK + .DCacheFetchLine, + .DCacheWriteLine, + .DCacheBusAck ); @@ -475,10 +475,10 @@ module lsu case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(DCRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(DCRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; - else if(DCFetchLine) BusNextState = STATE_BUS_FETCH; - else if(DCWriteLine) BusNextState = STATE_BUS_WRITE; + else if(DCacheRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(DCacheRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; + else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; @@ -498,24 +498,24 @@ module lsu assign CntReset = BusCurrState == STATE_BUS_READY; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCRWM)) | DCFetchLine | DCWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCacheRWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCRWM[0])) | + assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCacheRWM[0])) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCRWM[1])) | + assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCacheRWM[1])) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); - assign BUSACK = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | - (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | + (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCRWM & ~CacheableM)) | + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCacheRWM & ~CacheableM)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | From 2e5b805b0a24095ba05f75737801131a5564835e Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 29 Dec 2021 12:59:17 -0600 Subject: [PATCH 3/7] Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines Katherine/James --- wally-pipelined/config/buildroot/wally-config.vh | 3 +++ wally-pipelined/config/coremark/wally-config.vh | 3 +++ wally-pipelined/config/coremark_bare/wally-config.vh | 3 +++ wally-pipelined/config/fpga/wally-config.vh | 3 +++ wally-pipelined/config/rv32gc/wally-config.vh | 3 +++ wally-pipelined/config/rv32ic/wally-config.vh | 3 +++ wally-pipelined/config/rv64BP/wally-config.vh | 3 +++ wally-pipelined/config/rv64gc/wally-config.vh | 3 +++ wally-pipelined/config/rv64ic/wally-config.vh | 3 +++ 9 files changed, 27 insertions(+) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 1bf19b54e..53ea11538 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h0014112D) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index f26b6d2a7..fa089a3d9 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -35,6 +35,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000104) `define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index c357af64a..b7061fd52 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -35,6 +35,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000104) //`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) diff --git a/wally-pipelined/config/fpga/wally-config.vh b/wally-pipelined/config/fpga/wally-config.vh index 2e6b04944..c2ef2446b 100644 --- a/wally-pipelined/config/fpga/wally-config.vh +++ b/wally-pipelined/config/fpga/wally-config.vh @@ -37,6 +37,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h0014112D) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv32gc/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh index bcc42ec5f..06499180b 100644 --- a/wally-pipelined/config/rv32gc/wally-config.vh +++ b/wally-pipelined/config/rv32gc/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index b393119dd..36146e655 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 7a310bdfc..d29349012 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -37,6 +37,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000105) `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64gc/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh index 599d6d963..6f7dbd886 100644 --- a/wally-pipelined/config/rv64gc/wally-config.vh +++ b/wally-pipelined/config/rv64gc/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + // MISA RISC-V configuration per specification `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index d02fa871c..b4b93ed03 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + // MISA RISC-V configuration per specification `define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 From e36a037afa76abbc78f3ddd0487d42127611cc4a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 14:48:09 -0600 Subject: [PATCH 4/7] Added more generates around virtual memory and csrs in the lsu. --- wally-pipelined/regression/linux-wave.do | 139 +++++++++++------------ wally-pipelined/regression/wave.do | 87 +++++++------- wally-pipelined/src/lsu/lsu.sv | 88 ++++++++------ wally-pipelined/src/mmu/mmu.sv | 12 +- wally-pipelined/testbench/testbench.sv | 1 + 5 files changed, 173 insertions(+), 154 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 50306ffc5..2fed6c242 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -203,7 +203,7 @@ add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA @@ -220,19 +220,17 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb -add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width -add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState +add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/funct +add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/result +add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srca +add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srcb +add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/width +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FinalWriteDataM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable @@ -240,7 +238,7 @@ add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcac add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MemAdrE_RENAME @@ -249,13 +247,12 @@ add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/DCacheBusAdr +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/WordCount add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/IgnoreRequest -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ExceptionM add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} @@ -338,7 +335,6 @@ add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -ex add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay @@ -352,67 +348,64 @@ add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /t add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FinalWriteDataM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataWordM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/WordCount +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheFetchLine +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheWriteLine +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAck +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/Match -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/FirstMatch -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/R -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress @@ -504,7 +497,7 @@ add wave -noupdate /testbench/dut/hart/ifu/PCSrcE add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE add wave -noupdate /testbench/dut/hart/ieu/c/BranchE add wave -noupdate /testbench/dut/hart/ifu/PCLinkE -add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM +add wave -noupdate /testbench/dut/hart/lsu/LsuBusSize add wave -noupdate /testbench/dut/hart/ifu/PCF add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index e53e1a87c..afe2b0106 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -212,7 +212,7 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/BusCurrState add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState @@ -316,7 +316,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM r add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay @@ -334,50 +333,50 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheWriteLine add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAck add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/Match -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/FirstMatch -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/R -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index da35471f1..2a566d8b7 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -103,7 +103,6 @@ module lsu logic [11:0] LsuAdrE, DCacheAdrE; logic CPUBusy; logic MemReadM; - logic DataMisalignedM; logic DCacheStall; logic CacheableM; @@ -263,38 +262,65 @@ module lsu end endgenerate + // **** look into this confusing signal. assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; - mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(SelHPTW), - .PAdr(LsuPAdrM), - .VAdr(IEUAdrM), - .Size(LsuFunct3M[1:0]), - .PTE, - .PageTypeWriteVal(PageType), - .TLBWrite(DTLBWriteM), - .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), - .TLBMiss(DTLBMissM), - .Cacheable(CacheableM), - .Idempotent(), .AtomicAllowed(), - .TLBPageFault(DTLBPageFaultM), - .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, - .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), - .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW - ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? + generate + if(`ZICSR_SUPPORTED == 1) begin : dmmu + logic DataMisalignedM; + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) + dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .PrivilegeModeW, .DisableTranslation(SelHPTW), + .PAdr(LsuPAdrM), + .VAdr(IEUAdrM), + .Size(LsuFunct3M[1:0]), + .PTE, + .PageTypeWriteVal(PageType), + .TLBWrite(DTLBWriteM), + .TLBFlush(DTLBFlushM), + .PhysicalAddress(MemPAdrM), + .TLBMiss(DTLBMissM), + .Cacheable(CacheableM), + .Idempotent(), .AtomicAllowed(), + .TLBPageFault(DTLBPageFaultM), + .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, + .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug + .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW + ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? + + // Determine if an Unaligned access is taking place + // hptw guarantees alignment, only check inputs from IEU. + always_comb + case(Funct3M[1:0]) + 2'b00: DataMisalignedM = 0; // lb, sb, lbu + 2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu + 2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu + 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd + endcase + + // If the CPU's (not HPTW's) request is a page fault. + assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; + assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; + + end else begin + assign MemPAdrM = LsuPAdrM; + assign DTLBMissM = 0; + assign CacheableM = 1; + assign DTLBPageFaultM = 0; + assign LoadAccessFaultM = 0; + assign StoreMisalignedFaultM = 0; + assign LoadMisalignedFaultM = 0; + assign StoreMisalignedFaultM = 0; + end + endgenerate assign LSUStall = DCacheStall | InterlockStall | BusStall; - // If the CPU's (not HPTW's) request is a page fault. - assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; - assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; - // Move generate from lrsc to outside this module. + // use PreLsu as prefix for lrsc generate if (`A_SUPPORTED) begin assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; @@ -307,16 +333,6 @@ module lsu endgenerate - // Determine if an Unaligned access is taking place - // hptw guarantees alignment, only check inputs from IEU. - always_comb - case(Funct3M[1:0]) - 2'b00: DataMisalignedM = 0; // lb, sb, lbu - 2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu - 2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu - 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd - endcase - // conditional // 1. ram // controlled by `MEM_DTIM @@ -397,7 +413,7 @@ module lsu .ReadDataM); generate - if (`A_SUPPORTED) begin + if (`A_SUPPORTED) begin : amo logic [`XLEN-1:0] AMOResult; amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]), .result(AMOResult)); diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 8c6614a16..c9c130665 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -117,7 +117,17 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries /////////////////////////////////////////// pmachecker pmachecker(.*); - pmpchecker pmpchecker(.*); + + // if the number of entries is zero or no csr no pmp checker + generate + if(`PMP_ENTRIES > 0) begin : pmpchecker + pmpchecker pmpchecker(.*); + end else begin + assign PMPInstrAccessFaultF = 1'b0; + assign PMPLoadAccessFaultM = 1'b0; + assign PMPStoreAccessFaultM = 1'b0; + end + endgenerate // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 8234f6874..417bf7811 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -337,6 +337,7 @@ module riscvassertions; assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); + assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported."); end endmodule From aa227ce97c8d860aadc66b45185e74c4c982434e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 15:03:34 -0600 Subject: [PATCH 5/7] Changed names of lsu address signals. --- wally-pipelined/regression/linux-wave.do | 2 +- wally-pipelined/regression/wave.do | 2 +- .../src/cache/cachereplacementpolicy.sv | 10 +-- wally-pipelined/src/cache/dcache.sv | 16 ++--- wally-pipelined/src/cache/icache.sv | 2 +- wally-pipelined/src/lsu/lrsc.sv | 14 ++--- wally-pipelined/src/lsu/lsu.sv | 62 +++++++++---------- wally-pipelined/src/lsu/subwordread.sv | 12 ++-- wally-pipelined/testbench/testbench-linux.sv | 7 +-- 9 files changed, 63 insertions(+), 64 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 2fed6c242..734567ade 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -342,7 +342,7 @@ add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index afe2b0106..04df2d72f 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -322,7 +322,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index a0b774745..10e642a34 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -29,7 +29,7 @@ module cachereplacementpolicy (input logic clk, reset, input logic [NUMWAYS-1:0] WayHit, output logic [NUMWAYS-1:0] VictimWay, - input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrM, + input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrM, input logic [INDEXLEN-1:0] RAdr, input logic LRUWriteEn ); @@ -44,7 +44,7 @@ module cachereplacementpolicy logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacementD; - logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrMD; + logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrMD; logic [INDEXLEN-1:0] RAdrD; logic LRUWriteEnD; @@ -52,18 +52,18 @@ module cachereplacementpolicy always_ff @(posedge clk) begin if (reset) begin RAdrD <= '0; - MemPAdrMD <= '0; + LsuPAdrMD <= '0; LRUWriteEnD <= 0; NewReplacementD <= '0; for(int index = 0; index < NUMLINES; index++) ReplacementBits[index] <= '0; end else begin RAdrD <= RAdr; - MemPAdrMD <= MemPAdrM; + LsuPAdrMD <= LsuPAdrM; LRUWriteEnD <= LRUWriteEn; NewReplacementD <= NewReplacement; if (LRUWriteEnD) begin - ReplacementBits[MemPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD; + ReplacementBits[LsuPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD; end end end diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6d13a1a17..0023f97c9 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -37,7 +37,7 @@ module dcache input logic [1:0] AtomicM, input logic FlushDCacheM, input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] MemPAdrM, // physical address + input logic [`PA_BITS-1:0] LsuPAdrM, // physical address input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, @@ -124,7 +124,7 @@ module dcache mux3 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d2(FlushAdr), .s(SelAdrM), .y(RAdr)); @@ -134,7 +134,7 @@ module dcache .reset, .RAdr, .WAdr(RAdr), // *** Reduce after addressing in icache also - .PAdr(MemPAdrM), + .PAdr(LsuPAdrM), .WriteEnable(SRAMWayWriteEnable), .VDWriteEnable(VDWriteEnableWay), .WriteWordEnable(SRAMWordEnable), @@ -160,7 +160,7 @@ module dcache cachereplacementpolicy(.clk, .reset, .WayHit, .VictimWay, - .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .RAdr, .LRUWriteEn); end else begin @@ -191,12 +191,12 @@ module dcache // variable input mux - assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; + assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; // Write Path CPU (IEU) side onehotdecoder #(LOGWPL) - adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), + adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedW)); assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; @@ -216,8 +216,8 @@ module dcache .y(SRAMWriteData)); - mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .s({SelFlush, SelEvict}), .y(DCacheBusAdr)); diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index b46a91846..4b3000077 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -165,7 +165,7 @@ module icache cachereplacementpolicy(.clk, .reset, .WayHit, .VictimWay, - .MemPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .RAdr, .LRUWriteEn); // *** connect end else begin diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index 77e59cd37..3653f751a 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -31,10 +31,10 @@ module lrsc input logic clk, reset, input logic FlushW, CPUBusy, input logic MemReadM, - input logic [1:0] LsuRWM, - output logic [1:0] DCacheRWM, + input logic [1:0] PreLsuRWM, + output logic [1:0] LsuRWM, input logic [1:0] LsuAtomicM, - input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache + input logic [`PA_BITS-1:0] LsuPAdrM, // from mmu to dcache output logic SquashSCW ); // Handle atomic load reserved / store conditional @@ -44,16 +44,16 @@ module lrsc logic SquashSCM; assign lrM = MemReadM && LsuAtomicM[0]; - assign scM = LsuRWM[0] && LsuAtomicM[0]; - assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign scM = PreLsuRWM[0] && LsuAtomicM[0]; + assign WriteAdrMatchM = PreLsuRWM[0] && (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; - assign DCacheRWM = SquashSCM ? 2'b00 : LsuRWM; + assign LsuRWM = SquashSCM ? 2'b00 : PreLsuRWM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else ReservationValidM = ReservationValidW; // otherwise don't change valid end - flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LsuPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 2a566d8b7..7f49d32ce 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -90,16 +90,16 @@ module lsu logic DTLBPageFaultM; - logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache + logic [`PA_BITS-1:0] LsuPAdrM; // from mmu to dcache logic [`XLEN+1:0] IEUAdrExtM; logic DTLBMissM; logic DTLBWriteM; - logic [1:0] DCacheRWM; logic [1:0] LsuRWM; + logic [1:0] PreLsuRWM; logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; - logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; + logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr; logic [11:0] LsuAdrE, DCacheAdrE; logic CPUBusy; logic MemReadM; @@ -210,11 +210,11 @@ module lsu // arbiter between IEU and hptw // multiplex the outputs to LSU - mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); + mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); - mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); + mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM); assign CPUBusy = StallW & ~SelHPTW; @@ -224,16 +224,16 @@ module lsu // turns out because we cannot pipeline hptw requests we don't need this register //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle - //assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; + //assign PreLsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; - //assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; + //assign PreLsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; // Specify which type of page fault is occurring // *** `MEM_VIRTMEM - assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; + assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLsuRWM[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0]; assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; @@ -250,11 +250,11 @@ module lsu assign DTLBWriteM = 1'b0; assign ITLBWriteF = 1'b0; - assign LsuRWM = MemRWM; + assign PreLsuRWM = MemRWM; assign LsuFunct3M = Funct3M; assign LsuAtomicM = AtomicM; assign LsuAdrE = IEUAdrE[11:0]; - assign LsuPAdrM = IEUAdrExtM; + assign PreLsuPAdrM = IEUAdrExtM; assign CPUBusy = StallW; assign DTLBLoadPageFaultM = 1'b0; @@ -272,21 +272,21 @@ module lsu mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation(SelHPTW), - .PAdr(LsuPAdrM), + .PAdr(PreLsuPAdrM), .VAdr(IEUAdrM), .Size(LsuFunct3M[1:0]), .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), + .PhysicalAddress(LsuPAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), .TLBPageFault(DTLBPageFaultM), .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug - .WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), + .WriteAccessM(PreLsuRWM[0]), .ReadAccessM(PreLsuRWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? @@ -305,7 +305,7 @@ module lsu assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; end else begin - assign MemPAdrM = LsuPAdrM; + assign LsuPAdrM = PreLsuPAdrM; assign DTLBMissM = 0; assign CacheableM = 1; assign DTLBPageFaultM = 0; @@ -323,12 +323,12 @@ module lsu // use PreLsu as prefix for lrsc generate if (`A_SUPPORTED) begin - assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; - lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, - .SquashSCW, .DCacheRWM); + assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM, + .SquashSCW, .LsuRWM); end else begin assign SquashSCW = 0; - assign DCacheRWM = LsuRWM; + assign LsuRWM = PreLsuRWM; end endgenerate @@ -381,12 +381,12 @@ module lsu dcache dcache(.clk, .reset, .CPUBusy, - .MemRWM(DCacheRWM), + .MemRWM(LsuRWM), .Funct3M(LsuFunct3M), .Funct7M, .FlushDCacheM, .AtomicM(LsuAtomicM), .MemAdrE(DCacheAdrE), - .MemPAdrM, + .LsuPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), @@ -408,7 +408,7 @@ module lsu // finally swr subwordread subwordread(.ReadDataWordMuxM, - .MemPAdrM(MemPAdrM[2:0]), + .LsuPAdrM(LsuPAdrM[2:0]), .Funct3M(LsuFunct3M), .ReadDataM); @@ -423,7 +423,7 @@ module lsu endgenerate subwordwrite subwordwrite(.HRDATA(ReadDataWordM), - .HADDRD(MemPAdrM[2:0]), + .HADDRD(LsuPAdrM[2:0]), .HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}), .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); @@ -452,8 +452,8 @@ module lsu - //assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ; - assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : DCacheBusAdr ; + //assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ; + assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ; assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; @@ -491,8 +491,8 @@ module lsu case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(DCacheRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(DCacheRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; + else if(LsuRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(LsuRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; @@ -514,24 +514,24 @@ module lsu assign CntReset = BusCurrState == STATE_BUS_READY; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCacheRWM)) | DCacheFetchLine | DCacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCacheRWM[0])) | + assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCacheRWM[1])) | + assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCacheRWM & ~CacheableM)) | + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | diff --git a/wally-pipelined/src/lsu/subwordread.sv b/wally-pipelined/src/lsu/subwordread.sv index eaf2f94a9..beb1bf76f 100644 --- a/wally-pipelined/src/lsu/subwordread.sv +++ b/wally-pipelined/src/lsu/subwordread.sv @@ -28,7 +28,7 @@ module subwordread ( input logic [`XLEN-1:0] ReadDataWordMuxM, - input logic [2:0] MemPAdrM, + input logic [2:0] LsuPAdrM, input logic [2:0] Funct3M, output logic [`XLEN-1:0] ReadDataM ); @@ -42,7 +42,7 @@ module subwordread if (`XLEN == 64) begin // ByteMe mux always_comb - case(MemPAdrM[2:0]) + case(LsuPAdrM[2:0]) 3'b000: ByteM = ReadDataWordMuxM[7:0]; 3'b001: ByteM = ReadDataWordMuxM[15:8]; 3'b010: ByteM = ReadDataWordMuxM[23:16]; @@ -55,7 +55,7 @@ module subwordread // halfword mux always_comb - case(MemPAdrM[2:1]) + case(LsuPAdrM[2:1]) 2'b00: HalfwordM = ReadDataWordMuxM[15:0]; 2'b01: HalfwordM = ReadDataWordMuxM[31:16]; 2'b10: HalfwordM = ReadDataWordMuxM[47:32]; @@ -65,7 +65,7 @@ module subwordread logic [31:0] WordM; always_comb - case(MemPAdrM[2]) + case(LsuPAdrM[2]) 1'b0: WordM = ReadDataWordMuxM[31:0]; 1'b1: WordM = ReadDataWordMuxM[63:32]; endcase @@ -85,7 +85,7 @@ module subwordread end else begin // 32-bit // byte mux always_comb - case(MemPAdrM[1:0]) + case(LsuPAdrM[1:0]) 2'b00: ByteM = ReadDataWordMuxM[7:0]; 2'b01: ByteM = ReadDataWordMuxM[15:8]; 2'b10: ByteM = ReadDataWordMuxM[23:16]; @@ -94,7 +94,7 @@ module subwordread // halfword mux always_comb - case(MemPAdrM[1]) + case(LsuPAdrM[1]) 1'b0: HalfwordM = ReadDataWordMuxM[15:0]; 1'b1: HalfwordM = ReadDataWordMuxM[31:16]; endcase diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 091e1b25b..915ceee8a 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -49,6 +49,7 @@ module testbench(); ////////////////////////////////// HARDWARE /////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// logic clk, reset_ext; + logic reset; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end always begin clk <= 1; # 5; clk <= 0; # 5; end @@ -77,7 +78,7 @@ module testbench(); assign GPIOPinsIn = 0; assign UARTSin = 1; - wallypipelinedsoc dut(.clk, .reset_ext, + wallypipelinedsoc dut(.clk, .reset, .reset_ext, .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, @@ -85,8 +86,6 @@ module testbench(); .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); - logic reset; - assign reset = dut.reset; // Write Back stage signals not needed by Wally itself parameter nop = 'h13; @@ -446,7 +445,7 @@ module testbench(); end \ if(`"STAGE`"=="M") begin \ // override on special conditions \ - if (dut.hart.lsu.MemPAdrM == 'h10000005) \ + if (dut.hart.lsu.LsuPAdrM == 'h10000005) \ //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \ force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ else \ From ac5746c7213494d91ee585173cea8b39c7f6d5dc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 16:34:35 -0600 Subject: [PATCH 6/7] Name cleanup in LSU. --- wally-pipelined/regression/wave.do | 12 +++++++++--- wally-pipelined/src/lsu/lsu.sv | 15 +++++++++------ 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 04df2d72f..8cb29a8de 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -215,6 +215,13 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/BusCurrState add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusRead +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusWrite add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -468,9 +475,8 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChang add wave -noupdate /testbench/dut/hart/priv/priv/csr/MEPC_REGW add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr add wave -noupdate /testbench/dut/hart/lsu/BasePAdrMaskedM -add wave -noupdate /testbench/dut/hart/lsu/match TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35021 ns} 0} {{Cursor 4} {49574 ns} 1} +WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35522 ns} 0} {{Cursor 4} {49574 ns} 1} quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -486,4 +492,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {34887 ns} {35269 ns} +WaveRestoreZoom {35088 ns} {35954 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 7f49d32ce..74cf0d384 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -351,7 +351,7 @@ module lsu logic WordCountFlag; logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; - (* mark_debug = "true" *) logic [`XLEN-1:0] DC_HWDATA_FIXNAME; + (* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA; logic SelFlush; logic [`XLEN-1:0] ReadDataWordM; logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData; @@ -428,11 +428,10 @@ module lsu .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); - assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM; generate - if (`XLEN == 32) assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b010; - else assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b011; + if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010; + else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011; endgenerate; // Bus Side logic @@ -452,13 +451,17 @@ module lsu - //assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ; assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ; assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; - assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[WordCount]; + assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount]; + assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work. + + + + assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); assign CntEn = PreCntEn & LsuBusAck; From 56d86f4dd500ac8dbda0ceee7468d36738acf38d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 17:12:20 -0600 Subject: [PATCH 7/7] Moved LSU Bus interface control path into it's own module. --- wally-pipelined/regression/wave.do | 5 +- wally-pipelined/src/cache/dcache.sv | 3 +- wally-pipelined/src/lsu/busfsm.sv | 136 ++++++++++++++++++++++++++++ wally-pipelined/src/lsu/lsu.sv | 109 +++------------------- 4 files changed, 150 insertions(+), 103 deletions(-) create mode 100644 wally-pipelined/src/lsu/busfsm.sv diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 8cb29a8de..663a7deab 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -213,15 +213,13 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/BusCurrState +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusRead -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusWrite add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -474,7 +472,6 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextP add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate /testbench/dut/hart/priv/priv/csr/MEPC_REGW add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr -add wave -noupdate /testbench/dut/hart/lsu/BasePAdrMaskedM TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35522 ns} 0} {{Cursor 4} {49574 ns} 1} quietly wave cursor active 3 diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0023f97c9..92b468cef 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -53,8 +53,6 @@ module dcache output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], - output logic SelFlush, - input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, @@ -119,6 +117,7 @@ module dcache logic SelEvict; logic LRUWriteEn; logic [NUMWAYS-1:0] VDWriteEnableWay; + logic SelFlush; // Read Path CPU (IEU) side diff --git a/wally-pipelined/src/lsu/busfsm.sv b/wally-pipelined/src/lsu/busfsm.sv new file mode 100644 index 000000000..8eb70a036 --- /dev/null +++ b/wally-pipelined/src/lsu/busfsm.sv @@ -0,0 +1,136 @@ +/////////////////////////////////////////// +// busfsm.sv +// +// Written: Ross Thompson ross1728@gmail.com +// Modified: +// +// Purpose: Load/Store Unit's interface to BUS +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + + +module busfsm #(parameter integer WordCountThreshold, + parameter integer LOGWPL) + (input logic clk, + input logic reset, + + input logic IgnoreRequest, + input logic [1:0] LsuRWM, + input logic DCacheFetchLine, + input logic DCacheWriteLine, + input logic LsuBusAck, + input logic CPUBusy, + input logic CacheableM, + + output logic BusStall, + output logic LsuBusWrite, + output logic LsuBusRead, + output logic DCacheBusAck, + output logic BusCommittedM, + output logic SelUncachedAdr, + output logic [LOGWPL-1:0] WordCount); + + + + logic UnCachedLsuBusRead; + logic UnCachedLsuBusWrite; + logic CntEn, PreCntEn; + logic CntReset; + logic WordCountFlag; + logic [LOGWPL-1:0] NextWordCount; + + + typedef enum {STATE_BUS_READY, + STATE_BUS_FETCH, + STATE_BUS_WRITE, + STATE_BUS_UNCACHED_WRITE, + STATE_BUS_UNCACHED_WRITE_DONE, + STATE_BUS_UNCACHED_READ, + STATE_BUS_UNCACHED_READ_DONE, + STATE_BUS_CPU_BUSY} busstatetype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + + flopenr #(LOGWPL) + WordCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextWordCount), + .q(WordCount)); + + assign NextWordCount = WordCount + 1'b1; + + assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); + assign CntEn = PreCntEn & LsuBusAck; + + always_ff @(posedge clk) + if (reset) BusCurrState <= #1 STATE_BUS_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + case(BusCurrState) + STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; + else if(LsuRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(LsuRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; + else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; + else BusNextState = STATE_BUS_UNCACHED_WRITE; + STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; + else BusNextState = STATE_BUS_UNCACHED_READ; + STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_FETCH: if (WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_FETCH; + STATE_BUS_WRITE: if(WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_WRITE; + endcase + end + + + assign CntReset = BusCurrState == STATE_BUS_READY; + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) | + (BusCurrState == STATE_BUS_UNCACHED_WRITE) | + (BusCurrState == STATE_BUS_UNCACHED_READ) | + (BusCurrState == STATE_BUS_FETCH) | + (BusCurrState == STATE_BUS_WRITE); + assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; + assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) | + (BusCurrState == STATE_BUS_UNCACHED_WRITE); + assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); + + assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) | + (BusCurrState == STATE_BUS_UNCACHED_READ); + assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); + + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | + (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); + assign BusCommittedM = BusCurrState != STATE_BUS_READY; + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) | + (BusCurrState == STATE_BUS_UNCACHED_READ | + BusCurrState == STATE_BUS_UNCACHED_READ_DONE | + BusCurrState == STATE_BUS_UNCACHED_WRITE | + BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE); +endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 74cf0d384..d2207be02 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -342,17 +342,15 @@ module lsu localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; - localparam integer WordCountThreshold = WORDSPERLINE - 1; + localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); // temp - logic WordCountFlag; logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; (* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA; - logic SelFlush; logic [`XLEN-1:0] ReadDataWordM; logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData; @@ -360,12 +358,7 @@ module lsu logic [`XLEN-1:0] ReadDataWordMuxM; - logic [LOGWPL-1:0] WordCount, NextWordCount; - logic [`PA_BITS-1:0] BasePAdrMaskedM; - logic [OFFSETLEN-1:0] BasePAdrOffsetM; - logic CntEn, PreCntEn; - logic CntReset; logic [`PA_BITS-1:0] DCacheBusAdr; logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0]; @@ -375,8 +368,6 @@ module lsu logic DCacheFetchLine; logic DCacheBusAck; - logic UnCachedLsuBusRead; - logic UnCachedLsuBusWrite; logic SelUncachedAdr; @@ -393,7 +384,6 @@ module lsu .DCacheCommittedM, .DCacheBusAdr, .ReadDataBlockSetsM, - .SelFlush, .DCacheMemWriteData, .DCacheFetchLine, .DCacheWriteLine, @@ -401,6 +391,8 @@ module lsu ); + + // sub word selection for read and writes and optional amo alu. mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]), .s(SelUncachedAdr), @@ -429,15 +421,12 @@ module lsu .HWDATA(FinalWriteDataM)); - generate - if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010; - else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011; - endgenerate; // Bus Side logic // register the fetch data from the next level of memory. // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. + logic [LOGWPL-1:0] WordCount; genvar index; generate @@ -452,93 +441,19 @@ module lsu assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ; - assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; - assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount]; - assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work. + generate + if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010; + else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011; + endgenerate; - - - assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & LsuBusAck; - - flopenr #(LOGWPL) - WordCountReg(.clk(clk), - .reset(reset | CntReset), - .en(CntEn), - .d(NextWordCount), - .q(WordCount)); - - assign NextWordCount = WordCount + 1'b1; - - typedef enum {STATE_BUS_READY, - STATE_BUS_FETCH, - STATE_BUS_WRITE, - STATE_BUS_UNCACHED_WRITE, - STATE_BUS_UNCACHED_WRITE_DONE, - STATE_BUS_UNCACHED_READ, - STATE_BUS_UNCACHED_READ_DONE, - STATE_BUS_CPU_BUSY} busstatetype; - - (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; - - always_ff @(posedge clk) - if (reset) BusCurrState <= #1 STATE_BUS_READY; - else BusCurrState <= #1 BusNextState; - - always_comb begin - BusNextState = STATE_BUS_READY; - - case(BusCurrState) - STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(LsuRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(LsuRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; - else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; - STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; - else BusNextState = STATE_BUS_UNCACHED_WRITE; - STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; - else BusNextState = STATE_BUS_UNCACHED_READ; - STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_FETCH: if (WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_FETCH; - STATE_BUS_WRITE: if(WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_WRITE; - endcase - end - - - assign CntReset = BusCurrState == STATE_BUS_READY; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) | - (BusCurrState == STATE_BUS_UNCACHED_WRITE) | - (BusCurrState == STATE_BUS_UNCACHED_READ) | - (BusCurrState == STATE_BUS_FETCH) | - (BusCurrState == STATE_BUS_WRITE); - assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) | - (BusCurrState == STATE_BUS_UNCACHED_WRITE); - assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); - - assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) | - (BusCurrState == STATE_BUS_UNCACHED_READ); - assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); - - assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | - (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); - assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) | - (BusCurrState == STATE_BUS_UNCACHED_READ | - BusCurrState == STATE_BUS_UNCACHED_READ_DONE | - BusCurrState == STATE_BUS_UNCACHED_WRITE | - BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE); + busfsm #(WordCountThreshold, LOGWPL) + busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine, + .LsuBusAck, .CPUBusy, .CacheableM, .BusStall, .LsuBusWrite, .LsuBusRead, + .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); endmodule