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Fix icache for jumping into misaligned instructions

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This commit is contained in:
Jarred Allen 2021-03-16 16:57:51 -04:00
parent 98db312574
commit 3fc36b978d
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/ifu/icache.sv
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@ -51,7 +51,7 @@ module icache(
flopr #(1) flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle); flopr #(1) flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle);
flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF, DelayD); flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF, DelayD);
flopenr #(1) delaySideDFlop(clk, reset, ~StallF, DelaySideF, DelaySideD); flopenr #(1) delaySideDFlop(clk, reset, ~StallF, DelaySideF, DelaySideD);
flopenr #(1) delayStateFlop(clk, reset, ~StallF, DelayF & ~DelaySideF, DelaySideF); flopenrc#(1) delayStateFlop(clk, reset, FlushD, ~StallF, DelayF & ~DelaySideF, DelaySideF);
flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD); flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD);
// This flop is here to simulate pulling data out of the cache, which is edge-triggered // This flop is here to simulate pulling data out of the cache, which is edge-triggered