From ea85e185f1a5d477e4d7070b981397f1386d6abf Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 31 Jan 2022 00:59:44 +0000 Subject: [PATCH 1/2] gitmodules --- .gitmodules | 3 +++ addins/soc_flow | 1 + 2 files changed, 4 insertions(+) create mode 160000 addins/soc_flow diff --git a/.gitmodules b/.gitmodules index d434c3db8..05f44fd8a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -23,3 +23,6 @@ [submodule "addins/sky130_osu_sc_t18"] path = addins/sky130_osu_sc_t18 url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18 +[submodule "addins/soc_flow"] + path = addins/soc_flow + url = https://github.com/stineje/soc_flow diff --git a/addins/soc_flow b/addins/soc_flow new file mode 160000 index 000000000..60ca3dac1 --- /dev/null +++ b/addins/soc_flow @@ -0,0 +1 @@ +Subproject commit 60ca3dac1ae096740d3a6d19a5885f5f056ddb04 From 2d112698b762e2eb8d22442fa6f4f6e992e11345 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 31 Jan 2022 01:07:35 +0000 Subject: [PATCH 2/2] Replaced || and && with | and & --- .gitignore | 1 + addins/soc_flow | 2 +- examples/C/fir/Makefile | 2 +- examples/C/fir/fir | Bin 42704 -> 42704 bytes pipelined/config/rv32etim/wally-config.vh | 6 +-- pipelined/fpu-testfloat/FMA/tbgen/tb.sv | 46 +++++++++++----------- pipelined/src/fpu/cvtfp.sv | 2 +- pipelined/src/fpu/faddcvt.sv | 4 +- pipelined/src/fpu/fcvt.sv | 2 +- pipelined/src/fpu/fma.sv | 4 +- pipelined/src/fpu/fsm_fpdiv_pipe.sv | 8 ++-- pipelined/src/privileged/csrc.sv | 2 +- pipelined/testbench/sdc/sdModel.sv | 30 +++++++------- pipelined/testbench/testbench-linux.sv | 12 +++--- 14 files changed, 61 insertions(+), 60 deletions(-) diff --git a/.gitignore b/.gitignore index b745e3c63..047e9ed7a 100644 --- a/.gitignore +++ b/.gitignore @@ -51,4 +51,5 @@ fpga/generator/*.jou examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum +examples/C/fir/fir diff --git a/addins/soc_flow b/addins/soc_flow index 60ca3dac1..ba0cbc1d9 160000 --- a/addins/soc_flow +++ b/addins/soc_flow @@ -1 +1 @@ -Subproject commit 60ca3dac1ae096740d3a6d19a5885f5f056ddb04 +Subproject commit ba0cbc1d90e0aec296aed42fa87b20b9a575b5cf diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile index b1f4738cc..c27e423a5 100644 --- a/examples/C/fir/Makefile +++ b/examples/C/fir/Makefile @@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET) spike $(TARGET) $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ + riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ diff --git a/examples/C/fir/fir b/examples/C/fir/fir index f395b2e7e369d78774aea4c9e20a6e8cdab7c23a..4266f84b9d0a88a91abae47f9b0cd045d6ec5889 100755 GIT binary patch delta 100 zcmca`mg&M-rVWucq6&P53=9lBKrE&YB$!Kb3m6n9=h= `outDelay )) // outDelayCnt >= 4 (NCR) + if ((ValidCmd ) & (outDelayCnt >= `outDelay )) // outDelayCnt >= 4 (NCR) next_state = SEND_CMD; else if (inValidCmd) next_state = IDLE; @@ -387,7 +387,7 @@ module sdModel DATA_IDLE: begin if ((CardStatus[12:9]==`RCV) | (mult_write == 1'b1) ) next_datastate = READ_WAITS; - else if ((CardStatus[12:9]==`DATAS )|| (mult_read == 1'b1) ) + else if ((CardStatus[12:9]==`DATAS )| (mult_read == 1'b1) ) next_datastate = WRITE_DATA; else next_datastate = DATA_IDLE; @@ -551,7 +551,7 @@ module sdModel ResetCard; end 2 : begin //ALL_SEND_CARD_ID (CID) - if (lastCMD != 41 && outDelayCnt==0) begin + if (lastCMD != 41 & outDelayCnt==0) begin $fdisplay(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 2 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 2 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -561,7 +561,7 @@ module sdModel CardStatus[12:9] <=2; end 3 : begin //SEND_RELATIVE_CARD_ADDRESS (RCA) - if (lastCMD != 2 && outDelayCnt==0 ) begin + if (lastCMD != 2 & outDelayCnt==0 ) begin $fdisplay(sdModel_file_desc, "**Error in sequence, CMD 2 should precede 3 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, CMD 2 should precede 3 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -573,7 +573,7 @@ module sdModel cardIdentificationState<=0; end 6 : begin - if (lastCMD == 55 && outDelayCnt==0) begin //ACMD6 - SET_BUS_WIDTH + if (lastCMD == 55 & outDelayCnt==0) begin //ACMD6 - SET_BUS_WIDTH if (inCmd[9:8] == 2'b10) begin BusWidth <=4; $display(sdModel_file_desc, "**BUS WIDTH 4 ") ; @@ -627,7 +627,7 @@ module sdModel end 9 : begin // SEND_CARD_SPECIFIC_DATA (CSD) - if (lastCMD != 41 && outDelayCnt==0) begin + if (lastCMD != 41 & outDelayCnt==0) begin $fdisplay(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 9 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 9 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -743,7 +743,7 @@ module sdModel 41 : // CMD41 - SD_SEND_OCR begin if (cardIdentificationState) begin - if (lastCMD != 55 && outDelayCnt==0) begin // CMD41 - Reserved/Invalid + if (lastCMD != 55 & outDelayCnt==0) begin // CMD41 - Reserved/Invalid $fdisplay(sdModel_file_desc, "**Error in sequence, CMD 55 should precede 41 in Start-up state") ; $display( "**Error in sequence, CMD 55 should precede 41 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -755,7 +755,7 @@ module sdModel CardStatus[5] <=0; // not expecting next command to be ACMD if (Busy==1) CardStatus[12:9] <=1; // READY - end // else: !if(lastCMD != 55 && outDelayCnt==0) + end // else: !if(lastCMD != 55 & outDelayCnt==0) end // if (cardIdentificationState) end // case: 41 endcase // case (inCmd[45:40]) @@ -799,7 +799,7 @@ module sdModel else cmdOut<=1; - if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin + if ((cmdWrite>0) & (cmdWrite < response_S-8)) begin cmdOut<=response_CMD[135-cmdWrite]; crcIn<=response_CMD[134-cmdWrite]; if (cmdWrite >= response_S-9) @@ -948,7 +948,7 @@ module sdModel data_send_index<=1; // Next nibble is lower nibble end - else if ( (transf_cnt>=2) && (transf_cnt<=BLOCK_WIDTH -`CRC_OFF )) begin // if (2 <= transf_cnt <= 1025) + else if ( (transf_cnt>=2) & (transf_cnt<=BLOCK_WIDTH -`CRC_OFF )) begin // if (2 <= transf_cnt <= 1025) data_send_index<=~data_send_index; //toggle if (!data_send_index) begin //upper nibble if (BLOCK_WIDTH == 11'd1044) begin @@ -987,7 +987,7 @@ module sdModel if ( transf_cnt >=BLOCK_WIDTH-`CRC_OFF ) begin // if (trans_cnt >= 1025) crcDat_en<=0; // Disable CRC16 Generators end - end // if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) + end // if ( (transf_cnt>=2) & (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) else if (transf_cnt>BLOCK_WIDTH-`CRC_OFF & crc_c!=0) begin // if ((transf_cnt > 1025) and (crc_c /= 0)) datOut<= last_din; // if sent all data bitsbut not crc16 bits yet @@ -1004,7 +1004,7 @@ module sdModel else if (transf_cnt==BLOCK_WIDTH-2) begin // if (transf_cnt = 1042) Last CRC16 bit is 1041 datOut<=4'b1111; // send end bits end - else if ((transf_cnt !=0) && (crc_c == 0 ))begin // if sent data bits and crc_c points past last bit of CRC + else if ((transf_cnt !=0) & (crc_c == 0 ))begin // if sent data bits and crc_c points past last bit of CRC oeDat<=0; // disable output on DAT bus CardStatus[12:9] <= `TRAN; // put card in transfer state end @@ -1026,14 +1026,14 @@ module sdModel else if(flash_write_cnt == 2) datOut[0]<=0; - else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin + else if ((flash_write_cnt > 2) & (flash_write_cnt < 7)) begin if (crc_ok) datOut[0] <=okcrctoken[6-flash_write_cnt]; else datOut[0] <= invalidcrctoken[6-flash_write_cnt]; end - else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin + else if ((flash_write_cnt >= 7) & (flash_write_cnt < 264)) begin datOut[0]<=0; flash_blockwrite_cnt<=flash_blockwrite_cnt+2; @@ -1045,7 +1045,7 @@ module sdModel datOut<=1; InbuffStatus<=0; CardStatus[12:9] <= `TRAN; - end // else: !if((flash_write_cnt >= 7) && (flash_write_cnt < 264)) + end // else: !if((flash_write_cnt >= 7) & (flash_write_cnt < 264)) end // case: WRITE_FLASH endcase // case (dataState) end // always @ (negedge sdClk) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index b31140dd9..48cd4e891 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -379,7 +379,7 @@ module testbench; //$display("len = %d", line``STAGE.len()); \ for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ //$display("char = %s", line``STAGE[index]); \ - if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \ + if (line``STAGE[index``STAGE] == " " | line``STAGE[index``STAGE] == "\n") begin \ EndIndex``STAGE = index``STAGE; \ ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ @@ -412,7 +412,7 @@ module testbench; // parse CSRs, because there are 1 or more CSRs after the CSR token \ // we check if the CSR token or the number of CSRs is greater than 0. \ // if so then we want to parse for a CSR. \ - end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" | NumCSR``STAGE > 0) begin \ if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \ // all additional CSR's won't have this token. \ MarkerIndex``STAGE++; \ @@ -467,7 +467,7 @@ module testbench; // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); - if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.core.ieu.c.InstrValidM) begin + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately @@ -584,10 +584,10 @@ module testbench; if (MemOpW.substr(0,2) == "Mem") begin if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" || MemOpW == "MemRW") begin + if(MemOpW == "MemR" | MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin + end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end @@ -680,7 +680,7 @@ module testbench; PTE = dut.uncore.ram.ram.RAM[PAdr >> 3]; PTE_R = PTE[1]; PTE_X = PTE[3]; - if (PTE_R || PTE_X) begin + if (PTE_R | PTE_X) begin // Leaf page found break; end else begin