Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu

Browse Source
This commit is contained in:
Thomas Fleming 2021-04-01 16:23:19 -04:00
commit 3f3d8f414d
3 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/regression/wally-busybear-batch.do
View File

@ -26,7 +26,7 @@ vlib work-busybear
# suppress spurious warnngs about # suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time" # "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt # because vsim will run vopt
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
# start and run simulation # start and run simulation

2
wally-pipelined/regression/wally-busybear.do
View File

@ -26,7 +26,7 @@ vlib work-busybear
# suppress spurious warnngs about # suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time" # "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt # because vsim will run vopt
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
# start and run simulation # start and run simulation

5
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -145,7 +145,7 @@ module testbench_busybear();
integer regNumExpected; integer regNumExpected;
logic [`XLEN-1:0] PCW; logic [`XLEN-1:0] PCW;
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
genvar i; genvar i;
generate generate
@ -310,6 +310,7 @@ module testbench_busybear();
`define CSRM dut.hart.priv.csr.genblk1.csrm `define CSRM dut.hart.priv.csr.genblk1.csrm
`define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1 `define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
/*
//`CHECK_CSR(FCSR) //`CHECK_CSR(FCSR)
`CHECK_CSR2(MCAUSE, `CSRM) `CHECK_CSR2(MCAUSE, `CSRM)
`CHECK_CSR(MCOUNTEREN) `CHECK_CSR(MCOUNTEREN)
@ -335,6 +336,7 @@ module testbench_busybear();
`CHECK_CSR(SSTATUS) `CHECK_CSR(SSTATUS)
`CHECK_CSR2(STVAL, `CSRS) `CHECK_CSR2(STVAL, `CSRS)
`CHECK_CSR(STVEC) `CHECK_CSR(STVEC)
*/
initial begin //this is temporary until the bug can be fixed!!! initial begin //this is temporary until the bug can be fixed!!!
#11130100; #11130100;
@ -484,7 +486,6 @@ module testbench_busybear();
// Track names of instructions // Track names of instructions
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName); instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,