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https://github.com/openhwgroup/cvw
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Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
This commit is contained in:
commit
3f3d8f414d
@ -26,7 +26,7 @@ vlib work-busybear
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# suppress spurious warnngs about
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# because vsim will run vopt
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vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# start and run simulation
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@ -26,7 +26,7 @@ vlib work-busybear
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# suppress spurious warnngs about
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# because vsim will run vopt
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vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# start and run simulation
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@ -145,7 +145,7 @@ module testbench_busybear();
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integer regNumExpected;
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integer regNumExpected;
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logic [`XLEN-1:0] PCW;
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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genvar i;
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genvar i;
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generate
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generate
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@ -310,6 +310,7 @@ module testbench_busybear();
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`define CSRM dut.hart.priv.csr.genblk1.csrm
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`define CSRM dut.hart.priv.csr.genblk1.csrm
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`define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
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`define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
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/*
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//`CHECK_CSR(FCSR)
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//`CHECK_CSR(FCSR)
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`CHECK_CSR2(MCAUSE, `CSRM)
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`CHECK_CSR2(MCAUSE, `CSRM)
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`CHECK_CSR(MCOUNTEREN)
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`CHECK_CSR(MCOUNTEREN)
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@ -335,6 +336,7 @@ module testbench_busybear();
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`CHECK_CSR(SSTATUS)
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`CHECK_CSR(SSTATUS)
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`CHECK_CSR2(STVAL, `CSRS)
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`CHECK_CSR2(STVAL, `CSRS)
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`CHECK_CSR(STVEC)
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`CHECK_CSR(STVEC)
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*/
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initial begin //this is temporary until the bug can be fixed!!!
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initial begin //this is temporary until the bug can be fixed!!!
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#11130100;
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#11130100;
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@ -484,7 +486,6 @@ module testbench_busybear();
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// Track names of instructions
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
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instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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