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Started to integrate OSU divider

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David Harris 2021-02-17 15:38:44 -05:00
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1
wally-pipelined/src/muldiv/div/README Executable file
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vsim -do iter64.do -c

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wally-pipelined/src/muldiv/div/README.md Normal file
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This is a novel integer divider using r4 division by recurrence. The
reference is:
J. E. Stine and K. Hill, "An Efficient Implementation of Radix-4
Integer Division Using Scaling," 2020 IEEE 63rd International Midwest
Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA,
2020, pp. 1092-1095, doi: 10.1109/MWSCAS48704.2020.9184631.
Although this version does not contain scaling, it could do this, if
needed. Moreover, a higher radix or overlapped radix can be done
easily to expand the the size. Also, the implementations here are
initially unsigned but hope to expand for signed, which should be
easy.
There are two types of tests in this directory within each testbench.
One tests for 32-bits and the other 64-bits:
int32div.do and int64div.do = test individual vector for debugging
iter32.do and iter64.do = do not use any waveform generation and just
output lots of tests

1302
wally-pipelined/src/muldiv/div/divide4x32.sv Executable file
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1921
wally-pipelined/src/muldiv/div/divide4x64.sv Executable file
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114
wally-pipelined/src/muldiv/div/int32div.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog muxs.sv shifters.sv divide4x32.sv test_int32div.sv
# start and run simulation
vsim -voptargs=+acc work.tb
view list
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -noupdate -divider -height 32 "Control Signals"
add wave -hex -color gold /tb/clk
add wave -hex -color #0080ff /tb/reset
add wave -hex -color #0080ff /tb/start
add wave -hex -color #0080ff /tb/done
add wave -hex -color #0080ff /tb/divdone
add wave -noupdate -divider -height 32 "Key Parts"
add wave -unsigned /tb/dut/NumIter
add wave -unsigned /tb/dut/RemShift
add wave -unsigned /tb/dut/Qd2
add wave -unsigned /tb/dut/Rd2
add wave -unsigned /tb/dut/rem0
add wave -unsigned /tb/dut/Q
add wave -unsigned /tb/dut/P
add wave -unsigned /tb/dut/shiftResult
add wave -noupdate -divider -height 32 "FSM"
add wave -hex /tb/dut/fsm1/CURRENT_STATE
add wave -hex /tb/dut/fsm1/NEXT_STATE
add wave -hex -color #0080ff /tb/dut/fsm1/start
add wave -hex -color #0080ff /tb/dut/fsm1/state0
add wave -hex -color #0080ff /tb/dut/fsm1/done
add wave -hex -color #0080ff /tb/dut/fsm1/en
add wave -hex -color #0080ff /tb/dut/fsm1/divdone
add wave -hex -color #0080ff /tb/dut/fsm1/reset
add wave -hex -color #0080ff /tb/dut/fsm1/otfzero
add wave -hex -color #0080ff /tb/dut/fsm1/LT
add wave -hex -color #0080ff /tb/dut/fsm1/EQ
add wave -hex -color gold /tb/dut/fsm1/clk
add wave -noupdate -divider -height 32 "Datapath"
add wave -hex /tb/dut/N
add wave -hex /tb/dut/D
add wave -hex /tb/dut/reset
add wave -hex /tb/dut/start
add wave -hex /tb/dut/Q
add wave -hex /tb/dut/rem0
add wave -hex /tb/dut/div0
add wave -hex /tb/dut/done
add wave -hex /tb/dut/divdone
add wave -hex /tb/dut/enable
add wave -hex /tb/dut/state0
add wave -hex /tb/dut/V
add wave -hex /tb/dut/Num
add wave -hex /tb/dut/P
add wave -hex /tb/dut/NumIter
add wave -hex /tb/dut/RemShift
add wave -hex /tb/dut/op1
add wave -hex /tb/dut/op2
add wave -hex /tb/dut/op1shift
add wave -hex /tb/dut/Rem5
add wave -hex /tb/dut/Qd
add wave -hex /tb/dut/Rd
add wave -hex /tb/dut/Qd2
add wave -hex /tb/dut/Rd2
add wave -hex /tb/dut/quotient
add wave -hex /tb/dut/otfzero
add wave -noupdate -divider -height 32 "Divider"
add wave -hex -r /tb/dut/p3/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 138ns

114
wally-pipelined/src/muldiv/div/int64div.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog muxs.sv shifters.sv divide4x64.sv test_int64div.sv
# start and run simulation
vsim -voptargs=+acc work.tb
view list
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -noupdate -divider -height 32 "Control Signals"
add wave -hex -color gold /tb/clk
add wave -hex -color #0080ff /tb/reset
add wave -hex -color #0080ff /tb/start
add wave -hex -color #0080ff /tb/done
add wave -hex -color #0080ff /tb/divdone
add wave -noupdate -divider -height 32 "Key Parts"
add wave -unsigned /tb/dut/NumIter
add wave -unsigned /tb/dut/RemShift
add wave -unsigned /tb/dut/Qd2
add wave -unsigned /tb/dut/Rd2
add wave -unsigned /tb/dut/rem0
add wave -unsigned /tb/dut/Q
add wave -unsigned /tb/dut/P
add wave -unsigned /tb/dut/shiftResult
add wave -noupdate -divider -height 32 "FSM"
add wave -hex /tb/dut/fsm1/CURRENT_STATE
add wave -hex /tb/dut/fsm1/NEXT_STATE
add wave -hex -color #0080ff /tb/dut/fsm1/start
add wave -hex -color #0080ff /tb/dut/fsm1/state0
add wave -hex -color #0080ff /tb/dut/fsm1/done
add wave -hex -color #0080ff /tb/dut/fsm1/en
add wave -hex -color #0080ff /tb/dut/fsm1/divdone
add wave -hex -color #0080ff /tb/dut/fsm1/reset
add wave -hex -color #0080ff /tb/dut/fsm1/otfzero
add wave -hex -color #0080ff /tb/dut/fsm1/LT
add wave -hex -color #0080ff /tb/dut/fsm1/EQ
add wave -hex -color gold /tb/dut/fsm1/clk
add wave -noupdate -divider -height 32 "Datapath"
add wave -hex /tb/dut/N
add wave -hex /tb/dut/D
add wave -hex /tb/dut/reset
add wave -hex /tb/dut/start
add wave -hex /tb/dut/Q
add wave -hex /tb/dut/rem0
add wave -hex /tb/dut/div0
add wave -hex /tb/dut/done
add wave -hex /tb/dut/divdone
add wave -hex /tb/dut/enable
add wave -hex /tb/dut/state0
add wave -hex /tb/dut/V
add wave -hex /tb/dut/Num
add wave -hex /tb/dut/P
add wave -hex /tb/dut/NumIter
add wave -hex /tb/dut/RemShift
add wave -hex /tb/dut/op1
add wave -hex /tb/dut/op2
add wave -hex /tb/dut/op1shift
add wave -hex /tb/dut/Rem5
add wave -hex /tb/dut/Qd
add wave -hex /tb/dut/Rd
add wave -hex /tb/dut/Qd2
add wave -hex /tb/dut/Rd2
add wave -hex /tb/dut/quotient
add wave -hex /tb/dut/otfzero
add wave -noupdate -divider -height 32 "Divider"
add wave -hex -r /tb/dut/p3/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 138ns

50
wally-pipelined/src/muldiv/div/iter32.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog muxs.sv shifters.sv divide4x32.sv test_iter32.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 9586700ns
quit

50
wally-pipelined/src/muldiv/div/iter64.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog muxs.sv shifters.sv divide4x64.sv test_iter64.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 9586700ns
quit

51
wally-pipelined/src/muldiv/div/muxs.sv Normal file
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module mux2 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule // mux2
module mux3 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule // mux3
module mux4 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule // mux4
module mux21x32 (Z, A, B, Sel);
input logic [31:0] A;
input logic [31:0] B;
input logic Sel;
output logic [31:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x32
module mux21x64 (Z, A, B, Sel);
input logic [63:0] A;
input logic [63:0] B;
input logic Sel;
output logic [63:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x64

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wally-pipelined/src/muldiv/div/shifters.sv Normal file
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module shifter_l64 (Z, A, Shift);
input logic [63:0] A;
input logic [5:0] Shift;
logic [63:0] stage1;
logic [63:0] stage2;
logic [63:0] stage3;
logic [63:0] stage4;
logic [63:0] stage5;
logic [31:0] thirtytwozeros = 32'h0;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [63:0] Z;
mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]);
mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]);
mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]);
mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]);
mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]);
mux21x64 mx06(Z, stage5, {stage5[62:0], onezero}, Shift[0]);
endmodule // shifter_l64
module shifter_r64 (Z, A, Shift);
input logic [63:0] A;
input logic [5:0] Shift;
logic [63:0] stage1;
logic [63:0] stage2;
logic [63:0] stage3;
logic [63:0] stage4;
logic [63:0] stage5;
logic [31:0] thirtytwozeros = 32'h0;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [63:0] Z;
mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]);
mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]);
mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]);
mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]);
mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]);
mux21x64 mx06(Z, stage5, {onezero, stage5[63:1]}, Shift[0]);
endmodule // shifter_r64
module shifter_l32 (Z, A, Shift);
input logic [31:0] A;
input logic [4:0] Shift;
logic [31:0] stage1;
logic [31:0] stage2;
logic [31:0] stage3;
logic [31:0] stage4;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [31:0] Z;
mux21x32 mx01(stage1, A, {A[15:0], sixteenzeros}, Shift[4]);
mux21x32 mx02(stage2, stage1, {stage1[23:0], eightzeros}, Shift[3]);
mux21x32 mx03(stage3, stage2, {stage2[27:0], fourzeros}, Shift[2]);
mux21x32 mx04(stage4, stage3, {stage3[29:0], twozeros}, Shift[1]);
mux21x32 mx05(Z , stage4, {stage4[30:0], onezero}, Shift[0]);
endmodule // shifter_l32
module shifter_r32 (Z, A, Shift);
input logic [31:0] A;
input logic [4:0] Shift;
logic [31:0] stage1;
logic [31:0] stage2;
logic [31:0] stage3;
logic [31:0] stage4;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [31:0] Z;
mux21x32 mx01(stage1, A, {sixteenzeros, A[31:16]}, Shift[4]);
mux21x32 mx02(stage2, stage1, {eightzeros, stage1[31:8]}, Shift[3]);
mux21x32 mx03(stage3, stage2, {fourzeros, stage2[31:4]}, Shift[2]);
mux21x32 mx04(stage4, stage3, {twozeros, stage3[31:2]}, Shift[1]);
mux21x32 mx05(Z , stage4, {onezero, stage4[31:1]}, Shift[0]);
endmodule // shifter_r32

50
wally-pipelined/src/muldiv/div/test_int32div.sv Executable file
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module tb;
logic [31:0] N, D;
logic clk;
logic reset;
logic start;
logic [31:0] Q;
logic [31:0] rem;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
logic [7:0] count [0:15];
int32div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
#800 $finish;
end
initial
begin
#0 N = 32'h0;
#0 D = 32'h0;
#0 start = 1'b0;
#0 reset = 1'b1;
#22 reset = 1'b0;
//#25 N = 32'h9830_07C0;
//#0 D = 32'h0000_000C;
#25 N = 32'h06b9_7b0d;
#0 D = 32'h46df_998d;
#0 start = 1'b1;
#50 start = 1'b0;
end
endmodule // tb

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wally-pipelined/src/muldiv/div/test_int64div.sv Normal file
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module tb;
logic [63:0] N, D;
logic clk;
logic reset;
logic start;
logic [63:0] Q;
logic [63:0] rem;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
logic [7:0] count [0:15];
int64div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
#800 $finish;
end
initial
begin
#0 N = 64'h0;
#0 D = 64'h0;
#0 start = 1'b0;
#0 reset = 1'b1;
#22 reset = 1'b0;
//#25 N = 64'h0000_0000_9830_07C0;
//#0 D = 64'h0000_0000_0000_000C;
#25 N = 64'h0000_0000_06b9_7b0d;
#0 D = 64'h0000_0000_46df_998d;
#0 start = 1'b1;
#50 start = 1'b0;
end
endmodule // tb

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wally-pipelined/src/muldiv/div/test_iter32.sv Executable file
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module tb;
logic [31:0] N, D;
logic clk;
logic reset;
logic start;
logic [31:0] Q;
logic [31:0] rem0;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
bit [31:0] Ncomp;
bit [31:0] Dcomp;
bit [31:0] Qcomp;
bit [31:0] Rcomp;
logic [7:0] count [0:15];
int32div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("iter32.out");
#8000000 $finish;
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
for (i=0; i<2; i=i+1)
begin
N = $random;
D = $random;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (25)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
end
endmodule // tb

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wally-pipelined/src/muldiv/div/test_iter64.sv Executable file
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module tb;
logic [63:0] N, D;
logic clk;
logic reset;
logic start;
logic [63:0] Q;
logic [63:0] rem0;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
bit [63:0] Ncomp;
bit [63:0] Dcomp;
bit [63:0] Qcomp;
bit [63:0] Rcomp;
logic [7:0] count [0:15];
int64div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("iter64.out");
#8000000 $finish;
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
for (i=0; i<2; i=i+1)
begin
N = $random;
D = $random;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
end
endmodule // tb

10
wally-pipelined/src/muldiv/muldiv.sv
View File

@ -48,6 +48,16 @@ module muldiv (
mul mul(.*);
if (WIDTH==32) begin
divide4x32 div(.clk(clk), .reset(reset),
.N(SrcAE), .D(SrcBE), .Q(QuotE), .rem0(RemE),
.start(), .div0(), .done(), .divone());
end else begin // WIDTH=64
divide4x64 div(.clk(clk), .reset(reset),
.N(SrcAE), .D(SrcBE), .Q(QuotE), .rem0(RemE),
.start(), .div0(), .done(), .divone());
end
// Select result
always_comb
case (Funct3E)