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Remove verbosity from lsu state machine.

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Ross Thompson 2021-12-19 22:41:34 -06:00
parent d3c3422d12
commit 3eb5f33705
1 changed files with 27 additions and 72 deletions
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99
wally-pipelined/src/lsu/lsu.sv
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@ -150,76 +150,30 @@ module lsu
always_comb begin always_comb begin
case(CurrState) case(CurrState)
STATE_T0_READY: begin STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T3_DTLB_MISS;
if(~ITLBMissF & DTLBMissM & AnyCPUReqM) begin else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) NextState = STATE_T4_ITLB_MISS;
NextState = STATE_T3_DTLB_MISS; else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) NextState = STATE_T5_ITLB_MISS;
end else if(ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T7_DITLB_MISS;
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) begin else NextState = STATE_T0_READY;
NextState = STATE_T4_ITLB_MISS; STATE_T0_REPLAY: if(DCacheStall) NextState = STATE_T0_REPLAY;
end else NextState = STATE_T0_READY;
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) begin STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) NextState = STATE_T0_READY;
NextState = STATE_T5_ITLB_MISS; else if(DTLBWriteM) NextState = STATE_T0_REPLAY;
end else NextState = STATE_T3_DTLB_MISS;
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) begin STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) NextState = STATE_T0_READY;
NextState = STATE_T7_DITLB_MISS; else NextState = STATE_T4_ITLB_MISS;
end else begin STATE_T5_ITLB_MISS: if(ITLBWriteF) NextState = STATE_T0_REPLAY;
NextState = STATE_T0_READY; else if(WalkerInstrPageFaultRaw) NextState = STATE_T0_FAULT_REPLAY;
end else NextState = STATE_T5_ITLB_MISS;
end STATE_T0_FAULT_REPLAY: if(DCacheStall) NextState = STATE_T0_FAULT_REPLAY;
STATE_T0_REPLAY: begin else NextState = STATE_T0_READY;
if(DCacheStall) begin STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) NextState = STATE_T0_READY;
NextState = STATE_T0_REPLAY; else if(DTLBWriteM) NextState = STATE_T5_ITLB_MISS;
end else begin else NextState = STATE_T7_DITLB_MISS;
NextState = STATE_T0_READY; default: NextState = STATE_T0_READY;
end
end
STATE_T3_DTLB_MISS: begin
if(WalkerLoadPageFaultM | WalkerStorePageFaultM) begin
NextState = STATE_T0_READY;
end else if(DTLBWriteM) begin
NextState = STATE_T0_REPLAY;
end else begin
NextState = STATE_T3_DTLB_MISS;
end
end
STATE_T4_ITLB_MISS: begin
if(WalkerInstrPageFaultRaw | ITLBWriteF) begin
NextState = STATE_T0_READY;
end else begin
NextState = STATE_T4_ITLB_MISS;
end
end
STATE_T5_ITLB_MISS: begin
if(ITLBWriteF) begin
NextState = STATE_T0_REPLAY;
end else if(WalkerInstrPageFaultRaw) begin
NextState = STATE_T0_FAULT_REPLAY;
end else begin
NextState = STATE_T5_ITLB_MISS;
end
end
STATE_T0_FAULT_REPLAY: begin
if(DCacheStall) begin
NextState = STATE_T0_FAULT_REPLAY;
end else begin
NextState = STATE_T0_READY;
end
end
STATE_T7_DITLB_MISS: begin
if(WalkerStorePageFaultM | WalkerLoadPageFaultM) begin
NextState = STATE_T0_READY;
end else if(DTLBWriteM) begin
NextState = STATE_T5_ITLB_MISS;
end else begin
NextState = STATE_T7_DITLB_MISS;
end
end
default: begin
NextState = STATE_T0_READY;
end
endcase endcase
end // always_comb end // always_comb
// signal to CPU it needs to wait on HPTW. // signal to CPU it needs to wait on HPTW.
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
@ -330,12 +284,13 @@ module lsu
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0]; assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
// Determine if an Unaligned access is taking place // Determine if an Unaligned access is taking place
// hptw guarantees alignment, only check inputs from IEU.
always_comb always_comb
case(Funct3MtoDCache[1:0]) case(Funct3M[1:0])
2'b00: DataMisalignedM = 0; // lb, sb, lbu 2'b00: DataMisalignedM = 0; // lb, sb, lbu
2'b01: DataMisalignedM = MemPAdrNoTranslate[0]; // lh, sh, lhu 2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu
2'b10: DataMisalignedM = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu 2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
2'b11: DataMisalignedM = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd 2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
endcase endcase
// Determine if address is valid // Determine if address is valid