From 22fa6835858fb2829c19b9bac97a24823f658586 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 15:30:22 -0600
Subject: [PATCH 01/13] Added details about github cli to README.

---
 README.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/README.md b/README.md
index 92e4c638d..f957792a6 100644
--- a/README.md
+++ b/README.md
@@ -265,6 +265,17 @@ For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell li
 	$ cd cad/lib
 	$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
 
+### Install github cli
+
+The github cli allows users to directly issue pull requests from their fork back to openhwgroup/cvw using the command line.
+
+	$ type -p curl >/dev/null || sudo apt install curl -y
+	$ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ && sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
+	&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
+	&& sudo apt update \
+	&& sudo apt install gh -y
+
+
 ## Installing EDA Tools
 
 Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs.   Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text.  The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally.  It is anticipated that additional tools may be documented later after this is text is published to improve use and access.

From d835974774c24ba894277a3181fb6ccaad3264c6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 15:46:11 -0600
Subject: [PATCH 02/13] Added file to describe instructions on basic git fork
 work flow commands.

---
 gitflow.txt | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 gitflow.txt

diff --git a/gitflow.txt b/gitflow.txt
new file mode 100644
index 000000000..0be54022f
--- /dev/null
+++ b/gitflow.txt
@@ -0,0 +1,38 @@
+###########################################
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+Setup
+1. goto github and fork openhwgroup/cvw.git
+2. clone: git clone --recurse-submodules git@ross144/cvw.git
+3. git remote add upstream https://github.com/openhwgroup/cvw.git
+
+Once per sessiosn
+1. gh auth login
+2. Use ssh and point to your public key
+3. Copy one-time code from terminal to browser
+
+Fetch upstream and sync fork
+1. git fetch upstream
+2. git push
+
+Create pull request
+1. gh pr create
+2. Must include a title and strongly encourage a body message explaining your changes.
+3. Wait for pull request to be approved, rejected, or needs changes.
+4. Finish by fetching the upstream and pushing back to your fork.

From bce47dd3037a45dc15d3e1e025c40807493c66c1 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Mon, 23 Jan 2023 15:25:26 -0800
Subject: [PATCH 03/13] Update README.md

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 92e4c638d..74df28f56 100644
--- a/README.md
+++ b/README.md
@@ -67,9 +67,9 @@ The script installs the open source tools to /opt/riscv by default.  This can be
 
 	$ sudo wally-tool-chain-install.sh <optional, install directory, defaults to /opt/riscv>
 
-## Detailed Tool-chain Install Guide
+## Detailed Toolchain Install Guide
 
-   Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server.  This appendix describes how the system administrator installs RISC-V tools.  Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman.  
+This section describes how to install the tools needed for CORE-V-Wally. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so Appendix D also describes an option with a Docker container.  
 
 ### Open Source Software Installation
 

From bb11de0f4c31f8f135d5914dac815e5209b6c078 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 17:27:39 -0600
Subject: [PATCH 04/13] Another round of cleanup in the LSU.

---
 pipelined/src/lsu/lsu.sv | 170 +++++++++++++++++++--------------------
 1 file changed, 85 insertions(+), 85 deletions(-)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index d59934f55..ea3101c8b 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -32,107 +32,107 @@
 `include "wally-config.vh"
 
 module lsu (
-  input  logic             clk, reset,
-  input  logic             StallM, FlushM, StallW, FlushW,
-  output logic             LSUStallM,                               // LSU stalls pipeline during a multicycle operation
+  input  logic                clk,set,
+  input  logic                StallM,ushM, StallW, FlushW,
+  output logic                LSUStallM,                            // LSU stalls pipeline during a multicycle operation
   // connected to cpu (controls)
-  input  logic [1:0]       MemRWM,                                  // Read/Write control
-  input  logic [2:0]       Funct3M,                                 // Size of memory operation
-  input  logic [6:0]       Funct7M,                                 // Atomic memory operation function
-  input  logic [1:0]       AtomicM,                                 // Atomic memory operation
-  input  logic             FlushDCacheM,                            // Flush D cache to next level of memory
-  output logic             CommittedM,                              // Delay interrupts while memory operation in flight
-  output logic             SquashSCW,                               // Store conditional failed disable write to GPR
-  output logic             DCacheMiss,                              // D cache miss for performance counters
-  output logic             DCacheAccess,                            // D cache memory access for performance counters
+  input  logic [1:0]          MemRWM,                               // Read/Write control
+  input  logic [2:0]          Funct3M,                              // Size of memory operation
+  input  logic [6:0]          Funct7M,                              // Atomic memory operation function
+  input  logic [1:0]          AtomicM,                              // Atomic memory operation
+  input  logic                FlushDCacheM,                         // Flush D cache to next level of memory
+  output logic                CommittedM,                           // Delay interrupts while memory operation in flight
+  output logic                SquashSCW,                            // Store conditional failed disable write to GPR
+  output logic                DCacheMiss,                           // D cache miss for performance counters
+  output logic                DCacheAccess,                         // D cache memory access for performance counters
   // address and write data
-  input  logic [`XLEN-1:0] IEUAdrE,                                 // Execution stage memory address
-  output logic [`XLEN-1:0] IEUAdrM,       // Memory stage memory address
-  input logic [`XLEN-1:0] WriteDataM,     // Write data from IEU
-  output logic [`LLEN-1:0] ReadDataW,                               // Read data to IEU or FPU
+  input  logic [`XLEN-1:0]    IEUAdrE,                              // Execution stage memory address
+  output logic [`XLEN-1:0]    IEUAdrM,                              // Memory stage memory address
+  input  logic [`XLEN-1:0]    WriteDataM,                           // Write data from IEU
+  output logic [`LLEN-1:0]    ReadDataW,                            // Read data to IEU or FPU
   // cpu privilege
-  input  logic [1:0]       PrivilegeModeW,                          // Current privilege mode
-  input  logic             BigEndianM,                              // Swap byte order to big endian
-  input  logic             sfencevmaM,                              // Virtual memory address fence, invalidate TLB entries
+  input  logic [1:0]          PrivilegeModeW,                       // Current privilege mode
+  input  logic                BigEndianM,                           // Swap byte order to big endian
+  input  logic                sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
   // fpu
-  input  logic [`FLEN-1:0] FWriteDataM,                             // Write data from FPU
-  input  logic             FpLoadStoreM,                            // Selects FPU as store for write data
+  input  logic [`FLEN-1:0]    FWriteDataM,                          // Write data from FPU
+  input  logic                FpLoadStoreM,                         // Selects FPU as store for write data
   // faults
-  output logic             LoadPageFaultM, StoreAmoPageFaultM,      // Page fault exceptions
-  output logic             LoadMisalignedFaultM,                    // Load address misaligned fault
-  output logic             LoadAccessFaultM,                        // Load access fault (PMA)
-  output logic             HPTWInstrAccessFaultM,                   // HPTW generated access fault during instruction fetch
+  output logic                LoadPageFaultM,oreAmoPageFaultM,      // Page fault exceptions
+  output logic                LoadMisalignedFaultM,                 // Load address misaligned fault
+  output logic                LoadAccessFaultM,                     // Load access fault (PMA)
+  output logic                HPTWInstrAccessFaultM,                // HPTW generated access fault during instruction fetch
   // cpu hazard unit (trap)
-  output logic             StoreAmoMisalignedFaultM,                // Store or AMO address misaligned fault
-  output logic             StoreAmoAccessFaultM,                    // Store or AMO access fault
-          // connect to ahb
-  output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
-  input logic [`XLEN-1:0] HRDATA,       // Bus read data from LSU to EBU
-  output logic [`XLEN-1:0] LSUHWDATA,   // Bus write data from LSU to EBU
-  input logic LSUHREADY,                // Bus ready from LSU to EBU
-  output logic LSUHWRITE,               // Bus write operation from LSU to EBU
-  output logic [2:0] LSUHSIZE,          // Bus operation size from LSU to EBU
-  output logic [2:0] LSUHBURST,         // Bus burst from LSU to EBU
-  output logic [1:0] LSUHTRANS,         // Bus transaction type from LSU to EBU
-  output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
-          // page table walker
-  input  logic [`XLEN-1:0] SATP_REGW,                               // SATP (supervisor address translation and protection) CSR
-  input  logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
-  input  logic [1:0]       STATUS_MPP,                              // Machine previous privilege mode
-  input  logic [`XLEN-1:0] PCF,                                     // Fetch PC 
-  input  logic             ITLBMissF,                               // ITLB miss causes HPTW (hardware pagetable walker) walk
-  input  logic             InstrDAPageFaultF,                       // ITLB hit needs to update dirty or access bits
-  output logic [`XLEN-1:0] PTE,                                     // Page table entry write to ITLB
-  output logic [1:0]       PageType,                                // Type of page table entry to write to ITLB
-  output logic             ITLBWriteF,                              // Write PTE to ITLB
-  output logic             SelHPTW,                                 // During a HPTW walk the effective privilege mode becomes S_MODE
-  input var logic [7:0]    PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
+  output logic                StoreAmoMisalignedFaultM,             // Store or AMO address misaligned fault
+  output logic                StoreAmoAccessFaultM,                 // Store or AMO access fault
+  // connect to ahb
+  output logic [`PA_BITS-1:0] LSUHADDR,                             // Bus address from LSU to EBU
+  input  logic [`XLEN-1:0]    HRDATA,                               // Bus read data from LSU to EBU
+  output logic [`XLEN-1:0]    LSUHWDATA,                            // Bus write data from LSU to EBU
+  input  logic                LSUHREADY,                            // Bus ready from LSU to EBU
+  output logic                LSUHWRITE,                            // Bus write operation from LSU to EBU
+  output logic [2:0]          LSUHSIZE,                             // Bus operation size from LSU to EBU
+  output logic [2:0]          LSUHBURST,                            // Bus burst from LSU to EBU
+  output logic [1:0]          LSUHTRANS,                            // Bus transaction type from LSU to EBU
+  output logic [`XLEN/8-1:0]  LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
+  // page table walker
+  input  logic [`XLEN-1:0]    SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
+  input  logic                STATUS_MXR,ATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
+  input  logic [1:0]          STATUS_MPP,                           // Machine previous privilege mode
+  input  logic [`XLEN-1:0]    PCF,                                  // Fetch PC 
+  input  logic                ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
+  input  logic                InstrDAPageFaultF,                    // ITLB hit needs to update dirty or access bits
+  output logic [`XLEN-1:0]    PTE,                                  // Page table entry write to ITLB
+  output logic [1:0]          PageType,                             // Type of page table entry to write to ITLB
+  output logic                ITLBWriteF,                           // Write PTE to ITLB
+  output logic                SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[P_ENTRIES-1:0],     // PMP configuration from privileged unit
   input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]  // PMP address from privileged unit
 );
 
-  logic [`XLEN+1:0]         IEUAdrExtM;                              // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [`XLEN+1:0]         IEUAdrExtE;                              // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [`PA_BITS-1:0]      PAdrM;                                   // Physical memory address
-   logic [`XLEN+1:0] IHAdrM;               // Either IEU or HPTW memory address
+  logic [`XLEN+1:0]         IEUAdrExtM;                             // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [`XLEN+1:0]         IEUAdrExtE;                             // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [`PA_BITS-1:0]      PAdrM;                                  // Physical memory address
+  logic [`XLEN+1:0] 		IHAdrM;                                 // Either IEU or HPTW memory address
 
-  logic [1:0] 				PreLSURWM;                               // IEU or HPTW Read/Write signal
-  logic [1:0] 				LSURWM;                                  // IEU or HPTW Read/Write signal gated by LR/SC
-  logic [2:0]               LSUFunct3M;                              // IEU or HPTW memory operation size
-  logic [6:0]               LSUFunct7M;                              // AMO function gated by HPTW
-  logic [1:0]               LSUAtomicM;                              // AMO signal gated by HPTW
+  logic [1:0] 				PreLSURWM;                              // IEU or HPTW Read/Write signal
+  logic [1:0] 				LSURWM;                                 // IEU or HPTW Read/Write signal gated by LR/SC
+  logic [2:0]               LSUFunct3M;                             // IEU or HPTW memory operation size
+  logic [6:0]               LSUFunct7M;                             // AMO function gated by HPTW
+  logic [1:0]               LSUAtomicM;                             // AMO signal gated by HPTW
 
-  logic                     GatedStallW;                             // Hazard unit StallW gated when SelHPTW = 1
+  logic                     GatedStallW;                            // Hazard unit StallW gated when SelHPTW = 1
  
-  logic                     DCacheStallM;                            // D$ busy with multicycle operation
-  logic                     BusStall;                                // Bus interface busy with multicycle operation
-  logic                     HPTWStall;                               // HPTW busy with multicycle operation
+  logic                     DCacheStallM;                           // D$ busy with multicycle operation
+  logic                     BusStall;                               // Bus interface busy with multicycle operation
+  logic                     HPTWStall;                              // HPTW busy with multicycle operation
 
-  logic                     CacheableM;                              // PMA indicates memory address is cacheable
-  logic                     BusCommittedM;                           // Bus memory operation in flight, delay interrupts
-  logic 					DCacheCommittedM;                        // D$ memory operation started, delay interrupts
+  logic                     CacheableM;                             // PMA indicates memory address is cacheable
+  logic                     BusCommittedM;                          // Bus memory operation in flight, delay interrupts
+  logic 					DCacheCommittedM;                       // D$ memory operation started, delay interrupts
 
-  logic [`LLEN-1:0] 		DTIMReadDataWordM;                       // DTIM read data
-  logic [`LLEN-1:0] 		DCacheReadDataWordM;                     // D$ read data
-  logic [`LLEN-1:0] 		ReadDataWordMuxM;                        // DTIM or D$ read data
-  logic [`LLEN-1:0] 		LittleEndianReadDataWordM;               // Endian-swapped read data
-  logic [`LLEN-1:0] 		ReadDataWordM;                           // Read data before subword selection
-  logic [`LLEN-1:0]         ReadDataM;                               // Final read data
+  logic [`LLEN-1:0] 		DTIMReadDataWordM;                      // DTIM read data
+  logic [`LLEN-1:0] 		DCacheReadDataWordM;                    // D$ read data
+  logic [`LLEN-1:0] 		ReadDataWordMuxM;                       // DTIM or D$ read data
+  logic [`LLEN-1:0] 		LittleEndianReadDataWordM;              // Endian-swapped read data
+  logic [`LLEN-1:0] 		ReadDataWordM;                          // Read data before subword selection
+  logic [`LLEN-1:0]         ReadDataM;                              // Final read data
 
-  logic [`XLEN-1:0] 		IHWriteDataM;                            // IEU or HPTW write data
-  logic [`XLEN-1:0] 		IMAWriteDataM;                           // IEU, HPTW, or AMO write data
-  logic [`LLEN-1:0]         IMAFWriteDataM;                          // IEU, HPTW, AMO, or FPU write data
-  logic [`LLEN-1:0] 		LittleEndianWriteDataM;                  // Ending-swapped write data 
-  logic [`LLEN-1:0] 		LSUWriteDataM;                           // Final write data
-  logic [(`LLEN-1)/8:0]     ByteMaskM;                               // Selects which bytes within a word to write
+  logic [`XLEN-1:0] 		IHWriteDataM;                           // IEU or HPTW write data
+  logic [`XLEN-1:0] 		IMAWriteDataM;                          // IEU, HPTW, or AMO write data
+  logic [`LLEN-1:0]         IMAFWriteDataM;                         // IEU, HPTW, AMO, or FPU write data
+  logic [`LLEN-1:0] 		LittleEndianWriteDataM;                 // Ending-swapped write data 
+  logic [`LLEN-1:0] 		LSUWriteDataM;                          // Final write data
+  logic [(`LLEN-1)/8:0]     ByteMaskM;                              // Selects which bytes within a word to write
 
-  logic                     DTLBMissM;                               // DTLB miss causes HPTW walk
-  logic                     DTLBWriteM;                              // Writes PTE and PageType to DTLB
-  logic                     DataDAPageFaultM;                        // DTLB hit needs to update dirty or access bits
-  logic                     LSULoadAccessFaultM;                     // Load acces fault
-  logic 					LSUStoreAmoAccessFaultM;                 // Store access fault
-  logic                     IgnoreRequestTLB;                        // On either ITLB or DTLB miss, ignore miss so HPTW can handle
-  logic 					IgnoreRequest;                           // On FlushM or TLB miss ignore memory operation
-  logic                     SelDTIM;                                 // Select DTIM rather than bus or D$
+  logic                     DTLBMissM;                              // DTLB miss causes HPTW walk
+  logic                     DTLBWriteM;                             // Writes PTE and PageType to DTLB
+  logic                     DataDAPageFaultM;                       // DTLB hit needs to update dirty or access bits
+  logic                     LSULoadAccessFaultM;                    // Load acces fault
+  logic 					LSUStoreAmoAccessFaultM;                // Store access fault
+  logic                     IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
+  logic 					IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
+  logic                     SelDTIM;                                // Select DTIM rather than bus or D$
 
   
   /////////////////////////////////////////////////////////////////////////////////////////////

From a5d402c6ce38e03397427b88083ab01e00f8072e Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Mon, 23 Jan 2023 17:29:58 -0600
Subject: [PATCH 05/13] This adds the Dockerfile for those who might be
 interested in building a docker container for Wally

---
 addins/docker/Dockerfile | 107 +++++++++++++++++++++++++++++++++++++++
 addins/docker/README.md  |  48 ++++++++++++++++++
 2 files changed, 155 insertions(+)
 create mode 100755 addins/docker/Dockerfile
 create mode 100644 addins/docker/README.md

diff --git a/addins/docker/Dockerfile b/addins/docker/Dockerfile
new file mode 100755
index 000000000..e06fa039d
--- /dev/null
+++ b/addins/docker/Dockerfile
@@ -0,0 +1,107 @@
+# Compliance Development Environment Image
+FROM debian
+
+# UPDATE / UPGRADE
+RUN apt update
+
+# INSTALL
+RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
+
+RUN pip3 install chardet==3.0.4
+RUN pip3 install urllib3==1.22
+RUN pip3 install testresources
+RUN pip3 install riscof --ignore-installed PyYAML
+RUN echo "root:wally" | chpasswd
+
+# ADD RISCV
+WORKDIR /opt/riscv
+
+# Create a user group 'xyzgroup'
+ARG USERNAME=cad
+ARG USER_UID=1000
+ARG USER_GID=$USER_UID
+
+# Create the user
+RUN groupadd --gid $USER_GID $USERNAME \
+    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
+    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
+    && apt-get update \
+    && apt-get install -y sudo \
+    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
+    && chmod 0440 /etc/sudoers.d/$USERNAME
+
+# Change RISCV user
+run chown -Rf cad:cad /opt
+
+# Add cad user
+USER $USERNAME
+
+# SET ENVIRONMENT VARIABLES
+ENV RISCV=/opt/riscv
+ENV PATH=$PATH:$RISCV/bin
+
+# TOOLCHAIN
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
+    cd riscv-gnu-toolchain && \
+    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
+    make --jobs && \
+    make install
+
+# elf2hex
+ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+WORKDIR /opt/riscv
+RUN git clone https://github.com/sifive/elf2hex.git && \
+  cd elf2hex && \
+  autoreconf -i && \
+  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
+  make && \
+  make install
+
+# QEMU
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
+  cd qemu && \
+  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
+  make --jobs && \
+  make install
+
+# Spike
+WORKDIR /opt/riscv
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
+  mkdir riscv-isa-sim/build && \
+  cd riscv-isa-sim/build && \
+  ../configure --prefix=$RISCV --enable-commitlog && \
+  make --jobs && \
+  make install  && \
+  cd ../arch_test_target/spike/device && \
+  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
+  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
+
+# SAIL
+WORKDIR /opt/riscv
+RUN opam init -y --disable-sandboxing
+RUN opam switch create ocaml-base-compiler.4.06.1
+RUN opam install sail -y
+RUN eval $(opam config env) && \
+ cd $RISCV && \
+ git clone https://github.com/riscv/sail-riscv.git && \
+ cd sail-riscv && \
+ make && \
+ ARCH=RV32 make && \
+ ARCH=RV64 make && \
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \
+ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
+
+# Buildroot
+WORKDIR /opt/riscv
+RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git
+ENV export WALLY=/opt/riscv/riscv-wally
+RUN git clone https://github.com/buildroot/buildroot.git && \
+  cd buildroot && \
+  git checkout 2021.05 && \
+  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
+  cp ./board/wally/main.config .config && \
+  make --jobs
+
+# change to cad's hometown
+WORKDIR /home/cad
diff --git a/addins/docker/README.md b/addins/docker/README.md
new file mode 100644
index 000000000..135c7e744
--- /dev/null
+++ b/addins/docker/README.md
@@ -0,0 +1,48 @@
+Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages:
+
+-Building the executables takes several hours.
+-Linux is poorly standardized, and the build steps might not work on your version
+-The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
+
+Docker is a tools to run applications in a prepackaged container
+including all of the operating system support required.  Wally offers
+a ~30GB container image with the open-source tools pre-installed from
+Section D.1. In particular, using the container solves the long build
+time for gcc and the fussy installation of sail. The container runs on
+any platform supporting Docker, including Windows and Mac as well as
+Linux.  It can access files outside the container, including local
+installation of CAD tools such as Questa, and a local clone of the
+core-v-wally repository.
+
+Docker can be run on most operating systems, including Linux, Windows,
+and Mac. The Wally Docker container is hosted at DockerHub
+(http://docker.io).
+
+Podman is a more secure and easier-to-use variation of Docker for
+Linux developed by RedHat.  Both Docker and Podman run the same
+containers.
+
+This directory has a copy of the file utilized to create the Docker
+for the toolchain discussed in the text. To build this docker, you can
+type the following where the last argument is the name where you want
+to store your docker.
+
+docker build -t docker.io/wallysoc/wally-docker:latest .
+
+This can also be changed if you make a mistake by using the tag
+command.  For example, if I wanted to change my docker from
+wally-docker to wally-docker2, I would type:
+
+docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest
+
+Once you build your docker, you can run it as given in the Readme.
+However, you can also push it to DockerHub with the following command.
+
+docker push docker.io/wallysoc/wally-docker:latest
+
+To run your docker, you can type the following at a command prompt or
+terminal.
+
+docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker
+
+

From e1c121fe0d12a60533c00bf63d595dc75647ae9c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 17:38:30 -0600
Subject: [PATCH 06/13] Oups fixed bug from the last commit.

---
 pipelined/src/lsu/lrsc.sv |  9 +++++----
 pipelined/src/lsu/lsu.sv  | 10 +++++-----
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv
index 7edae6b81..c08c9f817 100644
--- a/pipelined/src/lsu/lrsc.sv
+++ b/pipelined/src/lsu/lrsc.sv
@@ -31,13 +31,14 @@
 `include "wally-config.vh"
 
 module lrsc(
-  input  logic                clk, reset,
+  input  logic                clk, 
+  input  logic                reset,
   input  logic                StallW,
-  input  logic                MemReadM,
+  input  logic                MemReadM,   // Memory read
   input  logic [1:0]          PreLSURWM,
   output logic [1:0]          LSURWM,
-  input  logic [1:0] 	        LSUAtomicM,
-  input  logic [`PA_BITS-1:0] PAdrM,  // from mmu to dcache
+  input  logic [1:0] 	      LSUAtomicM,
+  input  logic [`PA_BITS-1:0] PAdrM,      // from mmu to dcache
   output logic                SquashSCW
 );
 
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index ea3101c8b..f89fe0da4 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -32,8 +32,8 @@
 `include "wally-config.vh"
 
 module lsu (
-  input  logic                clk,set,
-  input  logic                StallM,ushM, StallW, FlushW,
+  input  logic                clk, reset,
+  input  logic                StallM, FlushM, StallW, FlushW,
   output logic                LSUStallM,                            // LSU stalls pipeline during a multicycle operation
   // connected to cpu (controls)
   input  logic [1:0]          MemRWM,                               // Read/Write control
@@ -58,7 +58,7 @@ module lsu (
   input  logic [`FLEN-1:0]    FWriteDataM,                          // Write data from FPU
   input  logic                FpLoadStoreM,                         // Selects FPU as store for write data
   // faults
-  output logic                LoadPageFaultM,oreAmoPageFaultM,      // Page fault exceptions
+  output logic                LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
   output logic                LoadMisalignedFaultM,                 // Load address misaligned fault
   output logic                LoadAccessFaultM,                     // Load access fault (PMA)
   output logic                HPTWInstrAccessFaultM,                // HPTW generated access fault during instruction fetch
@@ -77,7 +77,7 @@ module lsu (
   output logic [`XLEN/8-1:0]  LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
   // page table walker
   input  logic [`XLEN-1:0]    SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
-  input  logic                STATUS_MXR,ATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
+  input  logic                STATUS_MXR, STATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
   input  logic [1:0]          STATUS_MPP,                           // Machine previous privilege mode
   input  logic [`XLEN-1:0]    PCF,                                  // Fetch PC 
   input  logic                ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
@@ -86,7 +86,7 @@ module lsu (
   output logic [1:0]          PageType,                             // Type of page table entry to write to ITLB
   output logic                ITLBWriteF,                           // Write PTE to ITLB
   output logic                SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[P_ENTRIES-1:0],     // PMP configuration from privileged unit
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
   input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]  // PMP address from privileged unit
 );
 

From 45094fc7bbb88728125b3237d790bdeb6ee5f4f3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 17:46:28 -0600
Subject: [PATCH 07/13] Added comments to lrsc module.

---
 pipelined/src/lsu/lrsc.sv | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv
index c08c9f817..2fe8fb8ad 100644
--- a/pipelined/src/lsu/lrsc.sv
+++ b/pipelined/src/lsu/lrsc.sv
@@ -35,18 +35,19 @@ module lrsc(
   input  logic                reset,
   input  logic                StallW,
   input  logic                MemReadM,   // Memory read
-  input  logic [1:0]          PreLSURWM,
-  output logic [1:0]          LSURWM,
-  input  logic [1:0] 	      LSUAtomicM,
-  input  logic [`PA_BITS-1:0] PAdrM,      // from mmu to dcache
-  output logic                SquashSCW
+  input  logic [1:0]          PreLSURWM,  // Memory operation from the HPTW or IEU [1]: read, [0]: write
+  output logic [1:0]          LSURWM,     // Memory operation after potential squash of SC
+  input  logic [1:0] 	      LSUAtomicM, // Atomic memory operaiton
+  input  logic [`PA_BITS-1:0] PAdrM,      // Physical memory address 
+  output logic                SquashSCW   // Squash the store conditional by not allowing rf write
 );
 
+  // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
-  logic [`PA_BITS-1:2] 			  ReservationPAdrW;
-  logic 						          ReservationValidM, ReservationValidW; 
-  logic 						          lrM, scM, WriteAdrMatchM;
-  logic 						          SquashSCM;
+  logic [`PA_BITS-1:2] 		  ReservationPAdrW;
+  logic 					  ReservationValidM, ReservationValidW; 
+  logic 					  lrM, scM, WriteAdrMatchM;
+  logic 					  SquashSCM;
 
   assign lrM = MemReadM & LSUAtomicM[0];
   assign scM = PreLSURWM[0] & LSUAtomicM[0]; 

From 571f11938b76803ecf6eb0c7500f598314d37501 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 17:50:25 -0600
Subject: [PATCH 08/13] Updated gitflow instructions.

---
 gitflow.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gitflow.txt b/gitflow.txt
index 0be54022f..4198302aa 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -29,10 +29,14 @@ Once per sessiosn
 
 Fetch upstream and sync fork
 1. git fetch upstream
-2. git push
+2. git merge upstream/main
 
 Create pull request
 1. gh pr create
 2. Must include a title and strongly encourage a body message explaining your changes.
 3. Wait for pull request to be approved, rejected, or needs changes.
 4. Finish by fetching the upstream and pushing back to your fork.
+   1. git fetch upstream
+   2. git merge upstream/main
+   3. git push
+        

From 1d4c8c8a368e998699868bb8c896092d95d34715 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 17:50:25 -0600
Subject: [PATCH 09/13] Updated gitflow instructions.

---
 gitflow.txt | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/gitflow.txt b/gitflow.txt
index 0be54022f..3ff71a549 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -9,7 +9,7 @@
 ## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
 ## may obtain a copy of the License at
 ##
-## https:##solderpad.org/licenses/SHL-2.1/
+## https://solderpad.org/licenses/SHL-2.1/
 ##
 ## Unless required by applicable law or agreed to in writing, any work distributed under the 
 ## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
@@ -29,10 +29,17 @@ Once per sessiosn
 
 Fetch upstream and sync fork
 1. git fetch upstream
-2. git push
+2. git merge upstream/main
 
 Create pull request
-1. gh pr create
-2. Must include a title and strongly encourage a body message explaining your changes.
-3. Wait for pull request to be approved, rejected, or needs changes.
-4. Finish by fetching the upstream and pushing back to your fork.
+1. git fetch upstream
+2. git merge upstream/main
+3. git push
+4. gh pr create
+5. Must include a title and strongly encourage a body message explaining your changes.
+6. Wait for pull request to be approved, rejected, or needs changes.
+7. Finish by fetching the upstream and pushing back to your fork.
+   1. git fetch upstream
+   2. git merge upstream/main
+   3. git push
+        

From a9df0cf0106f4e37805483cb8100be3ccd22f9c1 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Mon, 23 Jan 2023 16:39:47 -0800
Subject: [PATCH 10/13] Update README.md

---
 README.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 52f6fe22d..12d7fe1f6 100644
--- a/README.md
+++ b/README.md
@@ -56,7 +56,7 @@ Run a regression simulation with Questa to prove everything is installed.
 	$ cd pipelined/regression
 	$ ./regression-wally       (depends on having Questa installed)
 
-# Tool-chain Installation (Sys Admin)
+# Toolchain Installation (Sys Admin)
 
 This section describes the open source toolchain installation.  These steps should only be done once by the system admin.
 
@@ -102,11 +102,11 @@ First, set up a directory for riscv software in some place such as /opt/riscv.
 
 ### Update Tools
 
-Ubuntu users may need to install and update various tools.
+Ubuntu users may need to install and update various tools.  Beware when cutting and pasting that some lines are long!
 
 	$ sudo apt update
 	$ sudo apt upgrade
-	$ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog 
+	$ sudo apt install git gawk make texinfo bison flex build-essential python3 zlib1g-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.0-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog 
 
 ### Install RISC-V GCC Cross-Compiler
 

From d495d7b04d96654fbe5d9930d45bc4edcd7f9b5b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 22:03:49 -0600
Subject: [PATCH 11/13] Added comments about needing move ebufsm into a new
 module.

---
 gitflow.txt              | 4 ++--
 pipelined/src/ebu/ebu.sv | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/gitflow.txt b/gitflow.txt
index 3ff71a549..b85324605 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -40,6 +40,6 @@ Create pull request
 6. Wait for pull request to be approved, rejected, or needs changes.
 7. Finish by fetching the upstream and pushing back to your fork.
    1. git fetch upstream
-   2. git merge upstream/main
-   3. git push
+   2. git merge upstream/main  # sync your clone with the upstream
+   3. git push                 # sync your fork with the upstream and clone
         
diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv
index 4a4cd5d5b..a75948023 100644
--- a/pipelined/src/ebu/ebu.sv
+++ b/pipelined/src/ebu/ebu.sv
@@ -144,6 +144,8 @@ module ebu (
   // a burst is completed.
   ////////////////////////////////////////////////////////////////////////////////////////////////////
 
+  // *** move into a separate module to match the figures 9.8 and 9.8
+
   assign both = LSUReq & IFUReq;
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
   always_comb 

From 89698a929e3215cc0e0ec57d42fe62020fe735e1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 23 Jan 2023 23:10:10 -0600
Subject: [PATCH 12/13] Moved ebufsmarb into its own module.

---
 pipelined/src/ebu/ebu.sv       |  76 ++-------------------
 pipelined/src/ebu/ebuarbfsm.sv | 121 +++++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+), 72 deletions(-)
 create mode 100644 pipelined/src/ebu/ebuarbfsm.sv

diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv
index a75948023..d4e87de2a 100644
--- a/pipelined/src/ebu/ebu.sv
+++ b/pipelined/src/ebu/ebu.sv
@@ -66,8 +66,6 @@ module ebu (
   output logic HMASTLOCK             // AHB master lock.  Wally does not use
 );
 
-  typedef enum                logic [1:0] {IDLE, ARBITRATE} statetype;
-  statetype                   CurrState, NextState;
 
   logic                       LSUDisable;
   logic 					  LSUSelect;
@@ -75,7 +73,6 @@ module ebu (
   logic 					  IFURestore;
   logic 					  IFUDisable;
   logic 					  IFUSelect;
-  logic                       both;                       // Both the LSU and IFU request at the same time
 
   logic [`PA_BITS-1:0]        IFUHADDROut;
   logic [1:0]                 IFUHTRANSOut;
@@ -92,12 +89,6 @@ module ebu (
   logic                       IFUReq;
   logic 					  LSUReq;
 
-  logic                       BeatCntEn;
-  logic [4-1:0]               NextBeatCount, BeatCount;   // Position within a burst transfer
-  logic                       FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
-  logic                       CntReset;
-  logic [3:0]                 Threshold;                  // Number of beats derived from HBURST
-  logic                       IFUReqD;                    // 1 cycle delayed IFU request. Part of arbitration
   
   
   assign HCLK = clk;
@@ -137,68 +128,9 @@ module ebu (
   assign HWSTRB = LSUHWSTRB;
   // HRDATA is sent to all controllers at the core level.
 
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Aribtration scheme
-  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
-  // a burst is completed.
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  // *** move into a separate module to match the figures 9.8 and 9.8
-
-  assign both = LSUReq & IFUReq;
-  flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
-  always_comb 
-    case (CurrState) 
-      IDLE: if (both)                                           NextState = ARBITRATE; 
-            else                                                NextState = IDLE;
-      ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq))  NextState = IDLE;
-                 else                                           NextState = ARBITRATE;
-      default:                                                  NextState = IDLE;
-    endcase
-
-  // basic arb always selects LSU when both
-  // replace this block for more sophisticated arbitration as needed.
-  // Controller 0 (IFU)
-  assign IFUSave = CurrState == IDLE & both;
-  assign IFURestore = CurrState == ARBITRATE;
-  assign IFUDisable = CurrState == ARBITRATE;
-  assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
-  // Controller 1 (LSU)
-  // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
-  // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
-  // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
-  // This is necessary because the pipeline is stalled for the entire duration of both transactions,
-  // and the LSU memory request will stil be active.
-  flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD);
-  assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
-  assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq;
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Burst mode logic
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount);  
-  assign NextBeatCount = BeatCount + 1'b1;
-
-  assign CntReset = NextState == IDLE;
-  assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
-  assign BeatCntEn = (NextState == ARBITRATE & HREADY);
-
-  // Used to store data from data phase of AHB.
-  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
-
-  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
-  always_comb begin
-    case(HBURST)
-      0:        Threshold = 4'b0000;
-      3:        Threshold = 4'b0011; // INCR4
-      5:        Threshold = 4'b0111; // INCR8
-      7:        Threshold = 4'b1111; // INCR16
-      default:  Threshold = 4'b0000; // INCR without end.
-    endcase
-  end
-  
-
+  ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave,
+		      .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect);
   
 endmodule
+
+
diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/pipelined/src/ebu/ebuarbfsm.sv
new file mode 100644
index 000000000..bd5cfb892
--- /dev/null
+++ b/pipelined/src/ebu/ebuarbfsm.sv
@@ -0,0 +1,121 @@
+///////////////////////////////////////////
+// ebufsmarb
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 23 January 2023
+// Modified: 23 January 2023
+//
+// Purpose: Arbitrates requests from instruction and data streams
+//          LSU has priority.
+// 
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ebufsmarb (
+  input  logic 	     HCLK,
+  input  logic 	     HRESETn,
+  input  logic [2:0] HBURST,
+ //  AHB burst length
+  
+  input  logic 	     HREADY,
+
+  input  logic 	     LSUReq,
+  input  logic 	     IFUReq,
+  
+  
+  output logic 	     IFUSave,
+  output logic 	     IFURestore,
+  output logic 	     IFUDisable,
+  output logic 	     IFUSelect,
+  output logic 	     LSUDisable,
+  output logic 	     LSUSelect);
+  
+  typedef enum 	     logic [1:0] {IDLE, ARBITRATE} statetype;
+  statetype          CurrState, NextState;
+
+  logic 	     both;                       // Both the LSU and IFU request at the same time
+  logic 	     IFUReqD;                    // 1 cycle delayed IFU request. Part of arbitration
+  logic 	     FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
+  logic 	     BeatCntEn;
+  logic [4-1:0]      NextBeatCount, BeatCount;   // Position within a burst transfer
+  logic 	     CntReset;
+  logic [3:0] 	     Threshold;                  // Number of beats derived from HBURST
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Aribtration scheme
+  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
+  // a burst is completed.
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  assign both = LSUReq & IFUReq;
+  flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
+  always_comb 
+    case (CurrState) 
+      IDLE: if (both)                                           NextState = ARBITRATE; 
+            else                                                NextState = IDLE;
+      ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq))  NextState = IDLE;
+                 else                                           NextState = ARBITRATE;
+      default:                                                  NextState = IDLE;
+    endcase
+
+  // basic arb always selects LSU when both
+  // replace this block for more sophisticated arbitration as needed.
+  // Controller 0 (IFU)
+  assign IFUSave = CurrState == IDLE & both;
+  assign IFURestore = CurrState == ARBITRATE;
+  assign IFUDisable = CurrState == ARBITRATE;
+  assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
+  // Controller 1 (LSU)
+  // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
+  // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
+  // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
+  // This is necessary because the pipeline is stalled for the entire duration of both transactions,
+  // and the LSU memory request will stil be active.
+  flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);
+  assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
+  assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq;
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Burst mode logic
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount);  
+  assign NextBeatCount = BeatCount + 1'b1;
+
+  assign CntReset = NextState == IDLE;
+  assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
+  assign BeatCntEn = (NextState == ARBITRATE & HREADY);
+
+  // Used to store data from data phase of AHB.
+  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
+
+  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
+  always_comb begin
+    case(HBURST)
+      0:        Threshold = 4'b0000;
+      3:        Threshold = 4'b0011; // INCR4
+      5:        Threshold = 4'b0111; // INCR8
+      7:        Threshold = 4'b1111; // INCR16
+      default:  Threshold = 4'b0000; // INCR without end.
+    endcase
+  end
+endmodule

From f37153cce879bd24b21c5ae856b9d75ae4edca3d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 24 Jan 2023 11:28:41 -0600
Subject: [PATCH 13/13] Clarified the git fork work flow.

---
 gitflow.txt | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/gitflow.txt b/gitflow.txt
index b85324605..bc89d2bf0 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -21,21 +21,29 @@ Setup
 1. goto github and fork openhwgroup/cvw.git
 2. clone: git clone --recurse-submodules git@ross144/cvw.git
 3. git remote add upstream https://github.com/openhwgroup/cvw.git
+4. install gh (github command line interface)
+type -p curl >/dev/null || sudo apt install curl -y
+curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \
+&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
+&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
+&& sudo apt update \
+&& sudo apt install gh -y
 
-Once per sessiosn
+Once per session (This authorizes gh to use your github account)
 1. gh auth login
 2. Use ssh and point to your public key
 3. Copy one-time code from terminal to browser
 
 Fetch upstream and sync fork
-1. git fetch upstream
-2. git merge upstream/main
+1. git fetch upstream                 # fetch the upstream openhwgroup/cvw into your local clone
+2. git merge upstream/main            # merge the upstream openhwgroup/cvw into your local clone
+3. git push                           # pushes changes back to your fork.  Now all three should be in sync
 
 Create pull request
-1. git fetch upstream
-2. git merge upstream/main
-3. git push
-4. gh pr create
+1. git fetch upstream                 # fetch the upstream openhwgroup/cvw into your local clone
+2. git merge upstream/main            # merge the upstream openhwgroup/cvw into your local clone
+3. git push                           # pushes changes back to your fork.  Now all three should be in sync
+4. gh pr create                       # Create a pull request.
 5. Must include a title and strongly encourage a body message explaining your changes.
 6. Wait for pull request to be approved, rejected, or needs changes.
 7. Finish by fetching the upstream and pushing back to your fork.