diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 700e945ae..aff5ac70d 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -127,7 +127,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) 
     CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
-    .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
+    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .InvalidateCache);
   if(NUMWAYS > 1) begin:vict
     cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
@@ -195,12 +195,13 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path: Write Enables
   /////////////////////////////////////////////////////////////////////////////////////////////
-  mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay, 
-    {SelFlush, SetValid}, SelectedWay);
+/* -----\/----- EXCLUDED -----\/-----
+  mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelectedWay);
   assign SetValidWay = SetValid ? SelectedWay : '0;
   assign ClearValidWay = ClearValid ? SelectedWay : '0;
   assign SetDirtyWay = SetDirty ? SelectedWay : '0;
   assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
+ -----/\----- EXCLUDED -----/\----- */
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Cache FSM
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index dec36cec8..38913bc44 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -38,10 +38,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   input logic [$clog2(NUMLINES)-1:0] CAdr,
   input logic [`PA_BITS-1:0]         PAdr,
   input logic [LINELEN-1:0]          LineWriteData,
-  input logic                        SetValidWay,
-  input logic                        ClearValidWay,
-  input logic                        SetDirtyWay,
-  input logic                        ClearDirtyWay,
+  input logic                        SetValid,
+  input logic                        ClearValid,
+  input logic                        SetDirty,
+  input logic                        ClearDirty,
   input logic                        SelEvict,
   input logic                        SelFlush,
   input logic                        VictimWay,
@@ -73,10 +73,27 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic                              SelectedWriteWordEn;
   logic [LINELEN/8-1:0]              FinalByteMask;
   logic                              SetValidEN;
+  logic                              SetValidWay;
+  logic                              ClearValidWay;
+  logic                              SetDirtyWay;
+  logic                              ClearDirtyWay;
+  logic                              SelectedWay;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Enable demux
   /////////////////////////////////////////////////////////////////////////////////////////////
+
+  mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid, SelectedWay);
+
+  // RT: Can we merge these two muxes?
+  //  mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelectedWay);
+  //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
+
+  assign SetValidWay = SetValid & SelectedWay;
+  assign ClearValidWay = ClearValid & SelectedWay;
+  assign SetDirtyWay = SetDirty & SelectedWay;
+  assign ClearDirtyWay = ClearDirty & SelectedWay;
+  
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
   assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR