Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/config/rv64ic/wally-config.vh

@@ -81,7 +81,7 @@
 `define BOOTTIM_RANGE  56'h00000FFF
 `define TIM_SUPPORTED 1'b1
 `define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h007FFFFF
+`define TIM_RANGE      56'h7FFFFFFF
 `define CLINT_SUPPORTED 1'b1
 `define CLINT_BASE  56'h02000000
 `define CLINT_RANGE 56'h0000FFFF

wally-pipelined/src/cache/dcache.sv

@@ -46,6 +46,8 @@ module dcache
    output logic [`XLEN-1:0]    ReadDataM, 
    output logic 	       DCacheStall,
    output logic 	       CommittedM,
+   output logic 	       DCacheMiss,
+   output logic 	       DCacheAccess,
 
    // inputs from TLB and PMA/P
    input logic 		       ExceptionM,
@@ -437,6 +439,8 @@ module dcache
     CommittedM = 1'b0;        
     SelUncached = 1'b0;
     SelEvict = 1'b0;
+    DCacheAccess = 1'b0;
+    DCacheMiss = 1'b0;
 
     case (CurrState)
       STATE_READY: begin
@@ -472,6 +476,7 @@ module dcache
 	// read hit valid cached
 	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  DCacheStall = 1'b0;
+	  DCacheAccess = 1'b1;
 	  
 	  if(StallW) begin
 	    NextState = STATE_CPU_BUSY;
@@ -485,6 +490,7 @@ module dcache
 	  DCacheStall = 1'b0;
 	  SRAMWordWriteEnableM = 1'b1;
 	  SetDirtyM = 1'b1;
+	  DCacheStall = 1'b1;
 	  
 	  if(StallW) begin 
 	    NextState = STATE_CPU_BUSY;
@@ -497,6 +503,8 @@ module dcache
 	  NextState = STATE_MISS_FETCH_WDV;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
+	  DCacheAccess = 1'b1;
+	  DCacheMiss = 1'b1;
 	end
 	// uncached write
 	else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin

wally-pipelined/src/fpu/fpu.sv

@@ -103,7 +103,6 @@ module fpu (
 	logic [63:0] 	   FMAResM, FMAResW;
 	logic [4:0] 	   FMAFlgM, FMAFlgW;
 	
-
 	logic [63:0] 	   ReadResW;
 	
 	// add/cvt signals
@@ -132,7 +131,6 @@ module fpu (
 	logic [63:0] 	   FPUResultW;                                           
 	logic [4:0] 	   FPUFlagsW;
 	
-
 	//DECODE STAGE
 	
 	// top-level controller for FPU
@@ -159,7 +157,6 @@ module fpu (
 				  {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD},
 				  {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE});
 	
-
 	//EXECUTION STAGE
 	
 	// Hazard unit for FPU
@@ -171,11 +168,19 @@ module fpu (
 	mux3  #(64)  fyemux(FRD2E, FPUResultW, FResM, FForwardYE, FSrcYE);
 	mux3  #(64)  fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FSrcZE);
 	
-      unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .ZFracE, .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
+	unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), 
+			    .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .XSgnE, .YSgnE, 
+			    .ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .ZFracE, 
+			    .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XNaNE, .YNaNE, .ZNaNE, 
+			    .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, 
+			    .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
       // first of two-stage instance of floating-point fused multiply-add unit
 	fma fma (.clk, .reset, .FlushM, .StallM, 
-               .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .ZFracE, .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, 
-               .XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XFracM, .YFracM, .ZFracM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
+		 .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XFracE, .YFracE, .
+		 ZFracE, .XAssumed1E, .YAssumed1E, .ZAssumed1E, .XDenormE, .YDenormE, 
+		 .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, 
+		 .XSgnM, .YSgnM, .ZSgnM, .XExpM, .YExpM, .ZExpM, .XFracM, 
+		 .YFracM, .ZFracM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
 		 //  .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM, 
 		 .FOpCtrlE(FOpCtrlE[2:0]), .FOpCtrlM(FOpCtrlM[2:0]), 
 		 .FmtE, .FmtM, .FrmM, .FMAFlgM, .FMAResM);
@@ -196,18 +201,24 @@ module fpu (
 				   .en(1'b1), .clear(FDivSqrtDoneE),
 				   .reset(reset),  .clk(HoldInputs));
 	//*** add round to nearest ties to max magnitude
-      fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .done(FDivSqrtDoneE), .rm(FrmE[1:0]),	.op_type(FOpCtrlE[0]), .P(~FmtE), .FDivBusyE, .HoldInputs, 
-                      .OvEn(1'b1), .UnEn(1'b1),	.start(FDivStartE), .reset, .clk(~clk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
+	fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .done(FDivSqrtDoneE), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), 
+			.P(~FmtE), .FDivBusyE, .HoldInputs, 
+			.OvEn(1'b1), .UnEn(1'b1),
+			.start(FDivStartE), .reset, .clk(~clk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
+	
         // .DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E, 
         //                 .FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM, 
         //                 .FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset);
 	// assign FDivBusyE = 0;
+	
 	// first of two-stage instance of floating-point add/cvt unit
 	faddcvt faddcvt (.clk, .reset, .FlushM, .StallM, .FrmM, .FOpCtrlM, .FmtE, .FmtM,
                          .FSrcXE, .FSrcYE, .FOpCtrlE, .FAddResM, .FAddFlgM);
 	
 	// first and only instance of floating-point comparator
-      fcmp fcmp (.op1({XSgnE,XExpE,XFracE}), .op2({YSgnE,YExpE,YFracE}), .FSrcXE, .FSrcYE, .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .Invalid(CmpNVE), .CmpResE, .XNaNE, .YNaNE, .XZeroE, .YZeroE);
+	fcmp fcmp (.op1({XSgnE,XExpE,XFracE}), .op2({YSgnE,YExpE,YFracE}), .FSrcXE, 
+		   .FSrcYE, .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, 
+		   .Invalid(CmpNVE), .CmpResE, .XNaNE, .YNaNE, .XZeroE, .YZeroE);
 	
 	// first and only instance of floating-point sign converter
 	fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .XExpE, .XFracE, .FmtE, .SgnResE, .SgnNVE, .XExpMaxE);
@@ -215,7 +226,6 @@ module fpu (
 	// first and only instance of floating-point classify unit
 	fclassify fclassify (.XSgnE, .XFracE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
 	
-
 	fcvt fcvt (.XSgnE, .XExpE, .XFracE, .XAssumed1E, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE);
 	
 	// output for store instructions
@@ -234,8 +244,6 @@ module fpu (
 				{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
 				{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
 	
-      
-     
 	flopenrc #(1)  EMRegCmp1(clk, reset, FlushM, ~StallM, CmpNVE, CmpNVM); 
 	flopenrc #(64) EMRegCmp2(clk, reset, FlushM, ~StallM, CmpResE, CmpResM); 
 	
@@ -266,15 +274,10 @@ module fpu (
 	// M/W pipe registers
 	//*****************
 	flopenrc #(64) MWRegFma1(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
-      
 	flopenrc #(64) MWRegDiv1(clk, reset, FlushW, ~StallW, FDivResultM, FDivResultW); 
-      
 	flopenrc #(64) MWRegAdd1(clk, reset, FlushW, ~StallW, FAddResM, FAddResW); 
-      
 	flopenrc #(64) MWRegCmp3(clk, reset, FlushW, ~StallW, CmpResM, CmpResW);
-
 	flopenrc #(64) MWRegClass2(clk, reset, FlushW, ~StallW, FResM, FResW);
-      
 	flopenrc #(6) MWCtrlReg(clk, reset, FlushW, ~StallW,
 				{FRegWriteM, FResultSelM, FmtM, FWriteIntM},
 				{FRegWriteW, FResultSelW, FmtW, FWriteIntW});
@@ -282,7 +285,6 @@ module fpu (
 	//#########################################
 	// BEGIN WRITEBACK STAGE
 	//#########################################
-
 	mux2  #(64)  ReadResMux({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
 	mux5  #(64)  FPUResultMux(ReadResW, FMAResW, FAddResW, FDivResultW, FResW, FResultSelW, FPUResultW);
 	

wally-pipelined/src/fpu/fsm.sv

@@ -6,7 +6,7 @@ module fsm (done, load_rega, load_regb, load_regc,
    input 	clk;
    input 	reset;
    input 	start;
-//    input 	error;
+   //    input 	error;
    input  	op_type;
    //***can use divbusy insted of holdinputs
    output       done;      
@@ -476,7 +476,7 @@ module fsm (done, load_rega, load_regb, load_regc,
 	       sel_muxa = 3'b011;
 	       sel_muxb = 3'b110;
 	       sel_muxr = 1'b1;
-	       NEXT_STATE = S26;
+	       NEXT_STATE = S27;
 	    end 
 	  S26:  // done
 	    begin

wally-pipelined/src/lsu/lsu.sv

@@ -45,6 +45,8 @@ module lsu
    output logic 	       CommittedM, 
    output logic 	       SquashSCW,
    output logic 	       DataMisalignedM,
+   output logic 	       DCacheMiss,
+   output logic 	       DCacheAccess,
 
    // address and write data
    input logic [`XLEN-1:0]     MemAdrM,
@@ -315,6 +317,8 @@ module lsu
 		.ReadDataM(HPTWReadPTE),
 		.DCacheStall(DCacheStall),
 		.CommittedM(CommittedMfromDCache),
+		.DCacheMiss,
+		.DCacheAccess,		
 		.ExceptionM(ExceptionM),
 		.PendingInterruptM(PendingInterruptMtoDCache),
 		.DTLBMissM(DTLBMissM),

wally-pipelined/src/privileged/csr.sv

@@ -46,6 +46,8 @@ module csr #(parameter
   input  logic 		   RASPredPCWrongM,
   input  logic 		   BPPredClassNonCFIWrongM,
   input  logic [4:0]       InstrClassM,
+  input  logic             DCacheMiss,
+  input  logic             DCacheAccess,
   input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
   input  logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
   input  logic             BreakpointFaultM, EcallFaultM,

wally-pipelined/src/privileged/csrc.sv

@@ -78,6 +78,8 @@ module csrc #(parameter
     input  logic             RASPredPCWrongM,
     input  logic             BPPredClassNonCFIWrongM,
     input  logic [4:0]       InstrClassM,
+    input  logic             DCacheMiss,
+    input  logic             DCacheAccess,
     input  logic [11:0]      CSRAdrM,
     input  logic [1:0]       PrivilegeModeW,
     input  logic [`XLEN-1:0] CSRWriteValM,
@@ -143,7 +145,9 @@ module csrc #(parameter
         assign CounterEvent[8] = RASPredPCWrongM & ~StallM;
         assign CounterEvent[9] = InstrClassM[3] & ~StallM;
         assign CounterEvent[10] = BPPredClassNonCFIWrongM & ~StallM;
-        assign CounterEvent[`COUNTERS-1:11] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+        assign CounterEvent[11] = DCacheAccess & ~StallM;
+        assign CounterEvent[12] = DCacheMiss & ~StallM;      
+        assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
 
         for (i = 3; i < `COUNTERS; i = i+1) begin
             assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);

wally-pipelined/src/privileged/privileged.sv

@@ -45,6 +45,8 @@ module privileged (
   input  logic 		   RASPredPCWrongM,
   input  logic 		   BPPredClassNonCFIWrongM,
   input  logic [4:0]       InstrClassM,
+  input  logic             DCacheMiss,
+  input  logic             DCacheAccess,
   input  logic             PrivilegedM,
   input  logic             ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
   input  logic             WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM,

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -164,6 +164,8 @@ module wallypipelinedhart
   
   logic 		    ExceptionM;
   logic 		    PendingInterruptM;
+  logic 		    DCacheMiss;
+  logic 		    DCacheAccess;
 
   
   ifu ifu(.InstrInF(InstrRData),
@@ -186,6 +188,8 @@ module wallypipelinedhart
 	  .ExceptionM(ExceptionM),
 	  .PendingInterruptM(PendingInterruptM),		
 	  .CommittedM(CommittedM),
+	  .DCacheMiss,
+          .DCacheAccess,
 	  .SquashSCW(SquashSCW),            
 	  .DataMisalignedM(DataMisalignedM),
 	  .MemAdrE(MemAdrE),