From 3ddf509f287de78d3956891471d14d6d03b1d8f3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:49:34 -0600 Subject: [PATCH] Renamed CPUBusy to Stall in cache. --- pipelined/src/cache/cachefsm.sv | 6 +++--- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 12fd3ade5..860432c82 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -40,7 +40,7 @@ module cachefsm input logic FlushCache, input logic InvalidateCache, // hazard inputs - input logic CPUBusy, + input logic Stall, // Bus inputs input logic CacheBusAck, // dcache internals @@ -130,7 +130,7 @@ module cachefsm //STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY; //else NextState = STATE_READY; - STATE_MISS_READ_DELAY: if(CPUBusy) NextState = STATE_MISS_READ_DELAY; + STATE_MISS_READ_DELAY: if(Stall) NextState = STATE_MISS_READ_DELAY; else NextState = STATE_READY; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV; else NextState = STATE_MISS_EVICT_DIRTY; @@ -201,6 +201,6 @@ module cachefsm resetDelay; assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY; - assign ce = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset; + assign ce = (CurrState == STATE_READY & ~Stall | CacheStall) | (CurrState != STATE_READY) | reset; endmodule // cachefsm diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 8da0dd51c..ba8ea1904 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -221,7 +221,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy, + icache(.clk, .reset, .FlushStage(TrapM), .Stall(CPUBusy), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e9ef4558a..920a9a22c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -254,7 +254,7 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .Stall(CPUBusy), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW,