diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 393f6ee11..ccc5928a5 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -55,11 +55,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -group {Memory Stage} /testbench/InstrMName @@ -85,11 +85,8 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE @@ -566,34 +563,12 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -609,4 +584,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {79760 ns} {171462 ns} +WaveRestoreZoom {117047 ns} {117181 ns} diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 42c484393..6f2cbd059 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -54,7 +54,8 @@ module RASPredictor #(parameter int StackSize = 16 logic DecrementPtr; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE; + // **********this part is wrong. + assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD); assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; assign PushE = InstrClassE[3] & ~StallM & ~FlushM; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6803f65d4..82bdf1f00 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,6 +28,8 @@ `include "wally-config.vh" +`define INSTR_CLASS_PRED 0 + module bpred ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -46,6 +48,8 @@ module bpred ( input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address + input logic [31:0] PostSpillInstrRawF, // Instruction + // Branch and jump outcome input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address @@ -63,13 +67,13 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [`XLEN-1:0] PredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; logic PredictionPCWrongE; logic PredictionInstrClassWrongE; - logic [3:0] InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic SelBPPredF; @@ -138,7 +142,7 @@ module bpred ( btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF, - .PredInstrClassF, + .BTBPredInstrClassF, .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, @@ -154,6 +158,36 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; // the branch predictor needs a compact decoding of the instruction class. + if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode + logic [4:0] CompressedOpcF; + logic [3:0] InstrClassF; + logic cjal, cj, cjr, cjalr; + + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + + assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | + (`C_SUPPORTED & CompressedOpcF == 5'h0e); + + assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + + assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + + assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); + assign PredInstrClassF = InstrClassF; + end else begin + assign PredInstrClassF = BTBPredInstrClassF; + end + + assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index a81af5bb4..9b6c66b85 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -38,7 +38,7 @@ module btb input logic StallF, StallD, StallM, FlushD, FlushM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC - output logic [3:0] PredInstrClassF, // BTB's guess at instruction class + output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong @@ -79,13 +79,13 @@ module btb flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} : + assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : MatchD ? {PredInstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; always_ff @ (posedge clk) begin if (reset) begin @@ -103,6 +103,6 @@ module btb .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f48727500..26227bb9b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -327,7 +327,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred