Updated figure cache references.

pipelined/src/cache/cache.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.11, and 7.20)
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //

pipelined/src/cache/cacheLRU.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Implements Pseudo LRU. Tested for Powers of 2.
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.16 to 7.19)
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //

pipelined/src/cache/cachefsm.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Controller for the dcache fsm
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.15 and Table 7.1)
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //

pipelined/src/cache/cacheway.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.12)
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //