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Continued framework for B instructions

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This commit is contained in:
David Harris 2023-01-20 14:27:13 -08:00
parent a968ae2f66
commit 3d13683c07
4 changed files with 11 additions and 2 deletions
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1
pipelined/testbench/testbench.sv
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@ -133,6 +133,7 @@ logic [3:0] dummy;
"wally32periph": tests = wally32periph; "wally32periph": tests = wally32periph;
"embench": tests = embench; "embench": tests = embench;
"coremark": tests = coremark; "coremark": tests = coremark;
"arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba;
endcase endcase
end end
if (tests.size() == 0) begin if (tests.size() == 0) begin

8
pipelined/testbench/tests.vh
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@ -944,6 +944,14 @@ string imperas32f[] = '{
"rv32i_m/Zifencei/src/Fencei.S" "rv32i_m/Zifencei/src/Fencei.S"
}; };
string arch32ba[] = '{
`RISCVARCHTEST,
// *** unclear why add.uw isn't in the list
"rv64i_m/B/src/sh1add-01.S",
"rv64i_m/B/src/sh1add-02.S",
"rv64i_m/B/src/sh1add-013.S"
};
string arch64m[] = '{ string arch64m[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/M/src/div-01.S", "rv64i_m/M/src/div-01.S",

2
tests/riscof/spike/spike_rv32imc_isa.yaml
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@ -1,6 +1,6 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
ISA: RV32IMAFDCZicsr_Zifencei ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
physical_addr_sz: 32 physical_addr_sz: 32
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [32] supported_xlen: [32]

2
tests/riscof/spike/spike_rv64gc_isa.yaml
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@ -1,6 +1,6 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
ISA: RV64IMAFDCSUZicsr_Zifencei ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
physical_addr_sz: 56 physical_addr_sz: 56
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [64] supported_xlen: [64]