diff --git a/.gitignore b/.gitignore index a01f1c07d..2acbd1f2a 100644 --- a/.gitignore +++ b/.gitignore @@ -42,6 +42,7 @@ tests/linux-testgen/buildroot-image-output tests/linux-testgen/buildroot-config-src/main.config.old tests/linux-testgen/buildroot-config-src/linux.config.old tests/linux-testgen/buildroot-config-src/busybox.config.old +linux/buildroot linux/testvector-generation/boottrace.S linux/testvector-generation/boottrace_disasm.log sim/slack-notifier/slack-webhook-url.txt diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6e7e4c8e9..74157bffa 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -69,9 +69,6 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249) -#git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13 -#./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13 ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} @@ -111,14 +108,15 @@ cd riscv-isa-sim/build make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device -sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include +# dh 2/5/24: these should be obsolete +#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include +#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Wally needs Verilator 5.021 or later. # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error) +sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g cd $RISCV git clone https://github.com/verilator/verilator # Only first time # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -173,6 +171,8 @@ sudo make install cd $RISCV opam init -y --disable-sandboxing +opam update +opam upgrade opam switch create 5.1.0 opam install sail -y diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 954c45d7d..6763f583c 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -95,7 +95,7 @@ localparam LOGR = $clog2(RADIX); // r = log(R localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated // intermediate division parameters not directly used in fdivsqrt hardware -localparam FPDIVMINb = NF + 3; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right +localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right //localparam FPDIVMINb = NF + 2 + (RADIX == 2); // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit for preshifting radix2 square root right, if radix4 doesn't use a right shift. This version saves one cycle on double-precision with R=4,k=4. However, it doesn't work yet because C is too short, so k is incorrectly calculated as a 1 in the lsb after the last step. localparam DIVMINb = ((FPDIVMINb= 64) AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access + else AccessByteOffsetM = 0; // shouldn't happen + 3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access + else AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; + default: AccessByteOffsetM = 0; // shouldn't happen endcase case (Funct3M[1:0]) - 2'b00: PotentialSpillM = '0; // byte access + 2'b00: PotentialSpillM = 0; // byte access 2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access 2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access 2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access - default: PotentialSpillM = '0; + default: PotentialSpillM = 0; endcase end - assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != '0); + assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != 0); assign ValidSpillM = MisalignedM & PotentialSpillM & ~CacheBusHPWTStall; // Don't take the spill if there is a stall @@ -118,20 +122,17 @@ module align import cvw::*; #(parameter cvw_t P) ( always_comb begin case (CurrState) - STATE_READY: if (ValidSpillM & ~MemRWM[0]) NextState = STATE_SPILL; // load spill - else if(ValidSpillM) NextState = STATE_STORE_DELAY; // store spill + STATE_READY: if (ValidSpillM) NextState = STATE_SPILL; // load spill else NextState = STATE_READY; // no spill STATE_SPILL: if(StallM) NextState = STATE_SPILL; else NextState = STATE_READY; - STATE_STORE_DELAY: NextState = STATE_SPILL; default: NextState = STATE_READY; endcase end - assign SelSpillM = (CurrState == STATE_SPILL | CurrState == STATE_STORE_DELAY); - assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY); + assign SelSpillM = CurrState == STATE_SPILL; + assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall); assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM; - assign SelStoreDelay = (CurrState == STATE_STORE_DELAY); // *** Can this be merged into the PreLSURWM logic? assign SpillStallM = SelSpillE; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -147,7 +148,7 @@ module align import cvw::*; #(parameter cvw_t P) ( // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit) // 8 * is for shifting by bytes not bits - assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate + assign ShiftAmount = SelHPTW ? 0 : {AccessByteOffsetM, 3'b0}; // AND gate assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount; assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0]; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index f53bb9296..9618e2cae 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -143,7 +143,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [(P.LLEN-1)/8:0] ByteMaskExtendedM; // Selects which bytes within a word to write logic [1:0] MemRWSpillM; logic SpillStallM; - logic SelStoreDelay; logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBWriteM; // Writes PTE and PageType to DTLB @@ -164,28 +163,27 @@ module lsu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); if(MISALIGN_SUPPORT) begin : ziccslm_align logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; - align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, + align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, .MemRWM, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, - .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM, - .SelStoreDelay); + .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; assign IEUAdrExtE = {2'b00, IEUAdrSpillE}; end else begin : no_ziccslm_align assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtE = {2'b00, IEUAdrE}; - assign SelSpillE = '0; + assign SelSpillE = 0; assign DCacheReadDataWordSpillM = DCacheReadDataWordM; assign ByteMaskSpillM = ByteMaskM; assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; - assign {SpillStallM, SelStoreDelay} = '0; + assign {SpillStallM} = 0; end if(P.ZICBOZ_SUPPORTED) begin : cboz - mux2 #(P.XLEN) writedatacbozmux(WriteDataM, '0, CMOpM[3], WriteDataZM); - end else begin : cboz + assign WriteDataZM = CMOpM[3] ? 0 : WriteDataM; + end else begin : cboz assign WriteDataZM = WriteDataM; end @@ -218,8 +216,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; - assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = 0; + assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = 0; end // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation. @@ -255,8 +253,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin // No MMU, so no PMA/page faults and no address translation - assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0; - assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0; + assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = 0; + assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = 0; assign PAdrM = IHAdrM[P.PA_BITS-1:0]; assign CacheableM = 1'b1; assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is @@ -281,7 +279,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr); - assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; + assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : 0; // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. // Add support for cboz @@ -318,22 +316,22 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.ZICBOZ_SUPPORTED) begin assign BusCMOZero = CMOpM[3] & ~CacheableM; - assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0; + assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : 0; assign BusAtomic = AtomicM[1] & ~CacheableM; end else begin - assign BusCMOZero = '0; - assign CacheCMOpM = '0; - assign BusAtomic = '0; + assign BusCMOZero = 0; + assign CacheCMOpM = 0; + assign BusAtomic = 0; end - assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0; + assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : 0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; - assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0; + assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : 0; assign FlushDCache = FlushDCacheM & ~(SelHPTW); cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), - .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), + .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataSpillM), .SelHPTW, @@ -367,7 +365,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface logic [1:0] BusRW; // Non-DTIM memory access, ignore cacheableM logic [P.XLEN-1:0] FetchBuffer; - assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; + assign BusRW = (~IgnoreRequestTLB & ~SelDTIM) ? LSURWM : 0; assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; @@ -381,14 +379,14 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats. assign LSUHBURST = 3'b0; - assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; + assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = 0; end end else begin: nobus // block: bus, only DTIM - assign LSUHWDATA = '0; + assign LSUHWDATA = 0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = '0; - assign {DCacheMiss, DCacheAccess} = '0; - assign {DCacheStallM, DCacheCommittedM} = '0; + assign {BusStall, BusCommittedM} = 0; + assign {DCacheMiss, DCacheAccess} = 0; + assign {DCacheStallM, DCacheCommittedM} = 0; end assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; @@ -417,7 +415,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Subword Accesses ///////////////////////////////////////////////////////////////////////////////////////////// - subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, + subwordread #(P) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[3:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM); diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index 82fb80fb1..a5ccd12bf 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -28,98 +28,47 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module subwordread #(parameter LLEN) - ( - input logic [LLEN-1:0] ReadDataWordMuxM, - input logic [2:0] PAdrM, - input logic [2:0] Funct3M, - input logic FpLoadStoreM, - input logic BigEndianM, - output logic [LLEN-1:0] ReadDataM +module subwordread import cvw::*; #(parameter cvw_t P) ( + input logic [P.LLEN-1:0] ReadDataWordMuxM, + input logic [3:0] PAdrM, + input logic [2:0] Funct3M, + input logic FpLoadStoreM, + input logic BigEndianM, + output logic [P.LLEN-1:0] ReadDataM ); + localparam ADRBITS = $clog2(P.LLEN)-3; + + logic [ADRBITS-1:0] PAdrSwapM; logic [7:0] ByteM; logic [15:0] HalfwordM; - logic [2:0] PAdrSwap; - // Funct3M[2] is the unsigned bit. mask upper bits. - // Funct3M[1:0] is the size of the memory access. - assign PAdrSwap = PAdrM ^ {3{BigEndianM}}; + logic [31:0] WordM; + logic [63:0] DblWordM; - if (LLEN == 64) begin:swrmux - // ByteMe mux - always_comb - case(PAdrSwap[2:0]) - 3'b000: ByteM = ReadDataWordMuxM[7:0]; - 3'b001: ByteM = ReadDataWordMuxM[15:8]; - 3'b010: ByteM = ReadDataWordMuxM[23:16]; - 3'b011: ByteM = ReadDataWordMuxM[31:24]; - 3'b100: ByteM = ReadDataWordMuxM[39:32]; - 3'b101: ByteM = ReadDataWordMuxM[47:40]; - 3'b110: ByteM = ReadDataWordMuxM[55:48]; - 3'b111: ByteM = ReadDataWordMuxM[63:56]; - endcase - - // halfword mux - always_comb - case(PAdrSwap[2:1]) - 2'b00: HalfwordM = ReadDataWordMuxM[15:0]; - 2'b01: HalfwordM = ReadDataWordMuxM[31:16]; - 2'b10: HalfwordM = ReadDataWordMuxM[47:32]; - 2'b11: HalfwordM = ReadDataWordMuxM[63:48]; - endcase - - logic [31:0] WordM; - - always_comb - case(PAdrSwap[2]) - 1'b0: WordM = ReadDataWordMuxM[31:0]; - 1'b1: WordM = ReadDataWordMuxM[63:32]; - endcase + // invert lsbs of address to select appropriate subword for big endian + if (P.BIGENDIAN_SUPPORTED) assign PAdrSwapM = PAdrM[ADRBITS-1:0] ^ {ADRBITS{BigEndianM}}; + else assign PAdrSwapM = PAdrM[ADRBITS-1:0]; - logic [63:0] DblWordM; - assign DblWordM = ReadDataWordMuxM[63:0]; + // Use indexed part select to imply muxes to select each size of subword + if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM); + else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM; + if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM); + else assign WordM = ReadDataWordMuxM; + mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM); + mux2 #(8) bytemux(HalfwordM[7:0], HalfwordM[15:8], PAdrSwapM[0], ByteM); - // sign extension/ NaN boxing - always_comb + // sign extension/ NaN boxing + always_comb case(Funct3M) - 3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - 3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw - 3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld - 3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu - //3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128 - 3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu - 3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu - default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen + 3'b000: ReadDataM = {{(P.LLEN-8){ByteM[7]}}, ByteM}; // lb + 3'b001: ReadDataM = {{P.LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + 3'b010: ReadDataM = {{P.LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw + 3'b011: if (P.LLEN >= 64) ReadDataM = {{P.LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld + else ReadDataM = ReadDataWordMuxM; // shouldn't happen + 3'b100: if (P.LLEN == 128) ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{P.LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq + else ReadDataM = {{P.LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{P.LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + 3'b110: ReadDataM = {{P.LLEN-32{1'b0}}, WordM[31:0]}; // lwu + default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase - - end else begin:swrmux // 32-bit - // byte mux - always_comb - case(PAdrSwap[1:0]) - 2'b00: ByteM = ReadDataWordMuxM[7:0]; - 2'b01: ByteM = ReadDataWordMuxM[15:8]; - 2'b10: ByteM = ReadDataWordMuxM[23:16]; - 2'b11: ByteM = ReadDataWordMuxM[31:24]; - endcase - - // halfword mux - always_comb - case(PAdrSwap[1]) - 1'b0: HalfwordM = ReadDataWordMuxM[15:0]; - 1'b1: HalfwordM = ReadDataWordMuxM[31:16]; - endcase - - // sign extension - always_comb - case(Funct3M) - 3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - 3'b010: ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw - 3'b011: ReadDataM = ReadDataWordMuxM; // fld - 3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu - default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen - endcase - end endmodule diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index 705672ff7..659d6d9c7 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -55,9 +55,9 @@ module subwordwrite #(parameter LLEN) ( end else begin:sww // 32-bit always_comb case(LSUFunct3M[1:0]) - 2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb - 2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh - 2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw + 2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb + 2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh + 2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen endcase end diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index 60164e081..d8db91cbc 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -42,7 +42,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8]; end else begin assign ByteMask = (('d2**('d2**Size))-'d1) << Adr; - assign ByteMaskExtended = '0; + assign ByteMaskExtended = 0; end /* Equivalent to the following diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 0823dc7e0..77e73e696 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -173,7 +173,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + //assign ReadDataNoXM = (ReadDataM[0] === 'x) ? 0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + assign ReadDataNoXM = ReadDataM; // *** temporary fix for synthesis; === and x in line above are not synthesizable. mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); @@ -212,9 +213,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( end else begin // block: hptwwrites assign NextPTE = ReadDataNoXM; assign HPTWAdr = HPTWReadAdr; - assign HPTWUpdateDA = '0; - assign UpdatePTE = '0; - assign HPTWRW[0] = '0; + assign HPTWUpdateDA = 0; + assign UpdatePTE = 0; + assign HPTWRW[0] = 0; end // Enable and select signals based on states diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 4a8712da9..d615d1370 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -98,6 +98,6 @@ module tlbmixer import cvw::*; #(parameter cvw_t P) ( // Output the hit physical address if translation is currently on. // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal - mux2 #(P.PA_BITS) hitmux('0, {PPNMixed2, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system + assign TLBPAdr = TLBHit ? {PPNMixed2, Offset} : 0; endmodule diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index 35b6f3fe6..fafc5c845 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -74,11 +74,11 @@ module csri import cvw::*; #(parameter cvw_t P) ( assign SIP_WRITE_MASK = 12'h000; assign MIE_WRITE_MASK = 12'h888; end - always @(posedge clk) + always_ff @(posedge clk) if (reset) MIP_REGW_writeable <= 12'b0; else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK); - always @(posedge clk) + always_ff @(posedge clk) if (reset) MIE_REGW <= 12'b0; else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 9f5b29428..35c27736c 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -163,7 +163,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); - end else assign MCOUNTEREN_REGW = '0; + end else assign MCOUNTEREN_REGW = 0; // MENVCFG register if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control @@ -199,7 +199,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( // verilator lint_off WIDTH logic [5:0] entry; always_comb begin - entry = '0; + entry = 0; CSRMReadValM = 0; IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 3a28c5075..733b2f0c6 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -66,7 +66,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = 0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index bc9f9235f..cf32c1f28 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -80,8 +80,8 @@ module privdec import cvw::*; #(parameter cvw_t P) ( if (P.U_SUPPORTED) begin:wfi logic [P.WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; - assign WFICountPlus1 = WFICount + 1; - floprc #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI + assign WFICountPlus1 = wfiM ? WFICount + 1 : '0; // restart counting on WFI + flopr #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, WFICountPlus1, WFICount); // count while in WFI // coverage off -item e 1 -fecexprrow 1 // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index f20604379..db31afa69 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -65,8 +65,8 @@ module trap import cvw::*; #(parameter cvw_t P) ( assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign Committed = CommittedM | CommittedF; - assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); - assign ValidIntsM = {12{~Committed}} & EnabledIntsM; + assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : 0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : 0); + assign ValidIntsM = Committed ? 0 : EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage. assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 691ba372d..961a50824 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -63,7 +63,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( // register access if (P.XLEN==64) begin:clint // 64-bit - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin case(entry) 16'h0000: PRDATA <= {63'b0, MSIP}; 16'h4000: PRDATA <= MTIMECMP; @@ -97,7 +97,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8]; end else MTIME <= MTIME + 1; end else begin:clint // 32-bit - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin case(entry) 16'h0000: PRDATA <= {31'b0, MSIP}; 16'h4000: PRDATA <= MTIMECMP[31:0]; diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 4c0602353..7858b2e35 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -91,7 +91,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( assign memread = ~PWRITE & PSEL; // read at start of access phase. PENABLE hasn't set up before this assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond assign entry = {PADDR[23:2],2'b0}; - assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. + assign One[P.PLIC_NUM_SRC-1:1] = 0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. @@ -104,13 +104,13 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // ================== localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31; - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin // resetting if (~PRESETn) begin - intPriority <= #1 '0; - intEn <= #1 '0; - intThreshold <= #1 '0; - intInProgress <= #1 '0; + intPriority <= #1 0; + intEn <= #1 0; + intThreshold <= #1 0; + intInProgress <= #1 0; // writing end else begin if (memwrite) diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index f8aa4e016..555a7682c 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -520,7 +520,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( intrpending = 0; end end - always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin + always_ff @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin // Side effect of reading LSR is lowering overrun, parity, framing, break intr's assign setSquashRXerrIP = ~MEMRb & (A==3'b101); diff --git a/synthDC/Makefile b/synthDC/Makefile index 7968a7b52..03c3c6612 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -51,7 +51,8 @@ configs: $(CONFIG) $(CONFIG): @echo $(CONFIG) cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) - cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) +# cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) + cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR) # adjust DTIM and IROM to reasonable values depending on config ifneq ($(filter $(CONFIG), $(DIRS32)),) @@ -61,8 +62,8 @@ else ifneq ($(filter $(CONFIG), $(DIRS64)),) sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh else - $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) - @echo "Config not in list, RAM_RANGE will be unmodified" + $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" endif # if USESRAM = 1, set that in the config file, otherwise reduce sizes diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 1b2402bee..c08b1d767 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -136,7 +136,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); // read line by line to count lines - if (ProgramAddrMapFP != '0) begin + if (ProgramAddrMapFP != 0) begin while (! $feof(ProgramAddrMapFP)) begin status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine; @@ -154,7 +154,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramLabelMapLineCount = 0; ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); - if (ProgramLabelMapFP != '0) begin + if (ProgramLabelMapFP != 0) begin while (! $feof(ProgramLabelMapFP)) begin status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine); ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine; @@ -174,7 +174,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( logic OrReducedAdr, AnyUnknown; assign OrReducedAdr = |ProgramAddrIndex; assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0; - initial ProgramAddrIndex = '0; + initial ProgramAddrIndex = 0; always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 746fde068..554ebc5d7 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -63,7 +63,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; logic wfiM; - logic InterruptM; + logic InterruptM, InterruptW; assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet @@ -231,7 +231,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end genvar index; - assign rf[0] = '0; + assign rf[0] = 0; for(index = 1; index < NUMREGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; @@ -239,7 +239,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3; always_comb begin - rf_wb <= '0; + rf_wb <= 0; if(rf_we3) rf_wb[rf_a3] <= 1'b1; end @@ -251,7 +251,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; always_comb begin - frf_wb <= '0; + frf_wb <= 0; if(frf_we4) frf_wb[frf_a4] <= 1'b1; end @@ -266,6 +266,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW); flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); + flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW); flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW); // **** remove? are these used? @@ -287,9 +288,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order assign rvvi.insn[0][0] = InstrRawW; assign rvvi.pc_rdata[0][0] = PCW; - assign rvvi.trap[0][0] = 0; + assign rvvi.trap[0][0] = TrapW; assign rvvi.halt[0][0] = HaltW; - assign rvvi.intr[0][0] = 0; + assign rvvi.intr[0][0] = InterruptW; assign rvvi.mode[0][0] = PrivilegeModeW; assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 : PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; @@ -492,7 +493,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end // *** implementation only cancel? so sc does not clear? - assign rvvi.lrsc_cancel[0][0] = '0; + assign rvvi.lrsc_cancel[0][0] = 0; integer index2; diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 1e2b760ca..296900b20 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -40,7 +40,7 @@ module watchdog #(parameter XLEN, WatchDogTimerThreshold) always_ff @(posedge clk) begin OldPCW <= PCW; if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; - else WatchDogTimerCount = '0; + else WatchDogTimerCount = 0; end always_comb begin diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv index 35e37f69f..27bcdb73e 100644 --- a/testbench/testbench-imperas.sv +++ b/testbench/testbench-imperas.sv @@ -252,9 +252,9 @@ module testbench; assign SDCCmdIn = SDCCmd; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ - assign SDCIntr = '0; + assign SDCIntr = 0; end else begin - assign SDCIntr = '0; + assign SDCIntr = 0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index 68d0ff3ef..2e7db3d6e 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -347,7 +347,7 @@ module testbench; if (P.UNCORE_RAM_SUPPORTED) begin `ifdef TB_UNCORE_RAM_SUPPORTED for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; `endif end if(reset) begin // branch predictor must always be reset @@ -423,7 +423,7 @@ module testbench; .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin assign HREADYEXT = 1; - assign {HRESPEXT, HRDATAEXT} = '0; + assign {HRESPEXT, HRDATAEXT} = 0; end if(P.FPGA) begin : sdcard @@ -436,8 +436,8 @@ module testbench; assign SDCCmdIn = SDCCmd; assign SDCDatIn = SDCDat; end else begin - assign SDCCmd = '0; - assign SDCDat = '0; + assign SDCCmd = 0; + assign SDCDat = 0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 036447341..b0255262f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -124,6 +124,7 @@ module testbench; "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; + "wally64q": if (P.Q_SUPPORTED) tests = wally64q; "wally64a": if (P.A_SUPPORTED) tests = wally64a; "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; @@ -452,7 +453,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -469,7 +470,7 @@ module testbench; .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin assign HREADYEXT = 1; - assign {HRESPEXT, HRDATAEXT} = '0; + assign {HRESPEXT, HRDATAEXT} = 0; end if(P.SDC_SUPPORTED) begin : sdcard @@ -485,9 +486,9 @@ module testbench; assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ - assign SDCIntr = '0; + assign SDCIntr = 0; end else begin - assign SDCIntr = '0; + assign SDCIntr = 0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/tests.vh b/testbench/tests.vh index fc04e9f7b..b611691db 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -869,6 +869,10 @@ string imperas32f[] = '{ "rv32i_m/I/XORI-01" }; + string wally64q[] = '{ + `WALLYTEST, + "rv64i_m/Q/src/WALLY-q-01.S" + }; string wally64a[] = '{ `WALLYTEST, diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 6ee45513f..f7e6b8c73 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,13 +2,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb -# ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x800000000015112D rv32: accessible: false rv64: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output new file mode 100644 index 000000000..6f8523bbf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output @@ -0,0 +1,36 @@ +00000000 # fsq of 1 +00000000 +00000000 +3fff0000 +dead4000 # fsh of 1 +deadbeef +deadbeef +deadbeef +00000000 # fsq of 3 +00000000 +00000000 +40008000 +00000000 # fsq of -1 +00000000 +00000000 +bfff0000 +00000000 # fsq of 6 +00000000 +00000000 +40018000 +00000000 # fsq of -4 +00000000 +00000000 +C0010000 +00000000 # fsq of -2 +00000000 +00000000 +C0000000 +00000000 # fsq of 4 +00000000 +00000000 +40010000 +00000000 # fsq of 2 +00000000 +00000000 +40000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S new file mode 100644 index 000000000..ea8bd15d5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S @@ -0,0 +1,154 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +// David_Harris@hmc.edu & Rose Thompson +// Created 07 March 2024 +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDQZfh_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*Q.*);def TEST_CASE_1=True;def NO_SAIL=True",flq-align) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +#endif + +# turn on the floating point unit +li x7, 1 +slli x7, x7, 13 +csrw mstatus, x7 + +li x4, 1 # 3fff 0000 0000 0000 0000 0000 0000 0000 +li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000 +fcvt.q.w f2, x2 +fcvt.q.w f4, x4 + +fcvt.h.w f5, x2 # 4000 + +# test quad load/store +fsq f4, 0(x3) +flq f7, 0(x3) +fsq f7, 0(x1) + +# test half load/store +fsh f5, 16(x3) +flh f6, 16(x3) +fsh f6, 16(x1) + +# 1 + 2 = 3 # 4000 8000 0000 0000 0000 0000 0000 0000 +fadd.q f8, f2, f4 +fsq f8, 32(x1) + +# 1 - 2 = -1 +fsub.q f9, f4, f2 # bfff 0000000000000000000000000000 +fsq f9, 48(x1) + +# 2 * 3 = 6 +fmul.q f10, f2, f8 # 4001 8000000000000000000000000000 +fsq f10, 64(x1) + +# 6 * (-1) + 2 = -4 +fmadd.q f11, f10, f9, f2 # C001 0000000000000000000000000000 +fsq f11, 80(x1) + +# -4 / 2 = -2 +fdiv.q f12, f11, f2 # C000 0000000000000000000000000000 +fsq f12, 96(x1) + +# sign injection (-4, 1) = 4 +fsgnj.q f13, f11, f4 # 4001 0000000000000000000000000000 +fsq f13, 112(x1) + +# sqrt(4) = 2 +fsqrt.q f14, f13 # 4000 0000000000000000000000000000 +fsq f14, 128(x1) + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +test_dataset_0: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_1: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: + + + + +signature_x1_1: + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef +rvtest_sig_end: +RVMODEL_DATA_END