diff --git a/bin/regression-wally b/bin/regression-wally
index a73f937a5..bf85b8225 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -32,18 +32,18 @@ tests = [
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", 
                     "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", 
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", 
-                    "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", 
-                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
+                    "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb",
+                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], #  "arch32zfad"  # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail
         ["rv64i", ["arch64i"]],
         ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
         ]
 
 # Separate out floating-point tests for RV64 to speed up coverage
 tests64gc_nofp = [
-        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",
+        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zcb",
                     "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", 
                     "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
-                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz"
+                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working:  "arch64zicboz"
     ]
 
 tests64gc_fp = [
@@ -261,7 +261,8 @@ testfloat = '--testfloat' in sys.argv
 
 if (nightly):
     nightMode = "--nightly";
-    sims = ["questa", "verilator", "vcs"]
+#    sims = ["questa", "verilator", "vcs"]
+    sims = ["verilator"] # *** uncomment to exercise all simulators
 else:
     nightMode = "";
     sims = [defaultsim]
@@ -386,7 +387,7 @@ def main():
         TIMEOUT_DUR = 60*1440 # 1 day
         #configs.append(getBuildrootTC(boot=False))
     elif '--testfloat' in sys.argv:
-        TIMEOUT_DUR = 60*60 # seconds
+        TIMEOUT_DUR = 5*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
         #configs.append(getBuildrootTC(boot=False))
diff --git a/sim/vcs/run_vcs.sh b/sim/vcs/run_vcs
similarity index 52%
rename from sim/vcs/run_vcs.sh
rename to sim/vcs/run_vcs
index ef9d84e45..334dbe43d 100755
--- a/sim/vcs/run_vcs.sh
+++ b/sim/vcs/run_vcs
@@ -1,15 +1,22 @@
 #!/bin/bash
+# VCS Compilation for WALLY
+# Divya Kohli, Rose Thompson, David Harris 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-
+CFG=${WALLY}/config
+SRC=${WALLY}/src 
+TB=${WALLY}/testbench
 # Set CONFIG_VARIANT from the first script argument
 #CONFIG_VARIANT=${1:-rv64i}
 CONFIG_VARIANT=${1}
 # Set TESTSUITE from the second script argument
 TESTSUITE=$2
-INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
-SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src" 
 
-SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv")  ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")" 
+
+INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
+SOURCE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" 
+
+SIMFILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_512x64.sv")  ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" 
 OUTPUT="sim_out"
 
 clean() {
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
index 47f5fb15f..deacdf5c2 100644
--- a/sim/verilator/Makefile
+++ b/sim/verilator/Makefile
@@ -1,3 +1,7 @@
+# Verilator Makefile for WALLY
+# Kunlin Han, Rose Thompson, David Harris 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 SHELL := /bin/bash
 .PHONY: profile run questa clean