From 3cae6ca90fea17c6d444877ac0d073fe4c35d8b1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Mar 2023 14:54:13 -0500
Subject: [PATCH] Updated NextAdr to NextSet.
---
src/cache/cache.sv | 8 ++++----
src/ifu/ifu.sv | 2 +-
src/lsu/lsu.sv | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index bea04a4d7..de3b8d711 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -39,7 +39,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic [1:0] CacheAtomic, // Atomic operation
input logic FlushCache, // Flush all dirty lines back to memory
input logic InvalidateCache, // Clear all valid bits
- input logic [11:0] NextAdr, // Virtual address, but we only use the lower 12 bits.
+ input logic [11:0] NextSet, // Virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] PAdr, // Physical address
input logic [(WORDLEN-1)/8:0] ByteMask, // Which bytes to write (D$ only)
input logic [WORDLEN-1:0] CacheWriteData, // Data to write to cache (D$ only)
@@ -50,7 +50,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
output logic CacheMiss, // Cache miss
output logic CacheAccess, // Cache access
// lsu control
- input logic SelHPTW, // Use PAdr from Hardware Page Table Walker rather than NextAdr
+ input logic SelHPTW, // Use PAdr from Hardware Page Table Walker rather than NextSet
// Bus fsm interface
input logic CacheBusAck, // Bus operation completed
input logic SelBusBeat, // Word in cache line comes from BeatCount
@@ -106,12 +106,12 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Read Path
/////////////////////////////////////////////////////////////////////////////////////////////
- // Choose read address (CacheSet). Normally use NextAdr, but use PAdr during stalls
+ // Choose read address (CacheSet). Normally use NextSet, but use PAdr during stalls
// and FlushAdr when handling D$ flushes
// The icache must update to the newest PCNextF on flush as it is probably a trap. Trap
// sets PCNextF to XTVEC and the icache must start reading the instruction.
assign AdrSelMuxSel = {SelFlush, ((SelAdr | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
- mux3 #(SETLEN) AdrSelMux(NextAdr[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
+ mux3 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSel, CacheSet);
// Array of cache ways, along with victim, hit, dirty, and read merging logic
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index d1d468aed..d8d48cbf4 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -245,7 +245,7 @@ module ifu (
.CacheWriteData('0),
.CacheRW(CacheRWF),
.CacheAtomic('0), .FlushCache('0),
- .NextAdr(PCSpillNextF[11:0]),
+ .NextSet(PCSpillNextF[11:0]),
.PAdr(PCPF),
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW)
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 4a53801b2..628c85bbd 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -266,7 +266,7 @@ module lsu (
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .READ_ONLY_CACHE(0)) dcache(
.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
- .FlushCache(FlushDCache), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
+ .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.CacheWriteData(LSUWriteDataM), .SelHPTW,
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),