diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index 17b1ede83..10b56f24e 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -97,11 +97,10 @@ localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
 localparam DIVN        = ((NF+2<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2; // standard length of input: max(XLEN, NF+2)
 localparam LOGR        = $clog2(RADIX);                             // r = log(R)
 localparam RK          = LOGR*DIVCOPIES;                            // r*k bits per cycle generated
-localparam LOGRK       = $clog2(RK);                                // log2(r*k)
-localparam FPDUR       = (DIVN+1)/RK + 1 + (RADIX/4);               // 
+localparam FPDUR       = (DIVN+1)/RK + 1 + (RADIX/4);               // *** relate to algorithm for rest of these
 localparam DURLEN      = $clog2(FPDUR+1);
 localparam DIVb        = FPDUR*RK - 1; // canonical fdiv size (b)
-localparam DIVBLEN     = $clog2(DIVb+2)-1;
+localparam DIVBLEN     = $clog2(DIVb+2)-1;                          // *** where is 2 coming from?
 
 // largest length in IEU/FPU
 localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));  // max(XLEN, NF)
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 0c377c02d..85c9d1c19 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -180,7 +180,6 @@ localparam cvw_t P = '{
   DIVN        : DIVN,
   LOGR        : LOGR,
   RK          : RK,
-  LOGRK       : LOGRK,
   FPDUR       : FPDUR,
   DURLEN      : DURLEN,
   DIVb        : DIVb,
diff --git a/src/cvw.sv b/src/cvw.sv
index 02105823e..3c32982bd 100644
--- a/src/cvw.sv
+++ b/src/cvw.sv
@@ -272,7 +272,6 @@ typedef struct packed {
   int DIVN       ;
   int LOGR       ;
   int RK         ;
-  int LOGRK      ;
   int FPDUR      ;
   int DURLEN     ;
   int DIVb       ;
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index e950a40bd..97ceeb085 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -133,9 +133,8 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
     assign ISpecialCaseE = BZeroE | ALTBE;
 
     // calculate right shift amount RightShiftX to complete in discrete number of steps
-    if (P.LOGRK > 0) begin // more than 1 bit per cycle
-      logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
-      logic [P.DIVBLEN:0] IntSteps;
+    if (P.RK > 1) begin // more than 1 bit per cycle
+      logic [$clog2(P.RK)-1:0] RightShiftX;
       /* verilator lint_offf WIDTH */
       assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
       assign DivXShifted = DivX >> RightShiftX;                     // shift X by up to R*K-1 to complete in n steps