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tentatively remade test lib to use macros for more flexibility
This commit is contained in:
Kip Macsai-Goren
parent
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commit
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@ -0,0 +1,560 @@
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///////////////////////////////////////////
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//
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// WALLY-TEST-LIB-64.h
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-01-30
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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.macro INIT_TESTS
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64I")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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// ---------------------------------------------------------------------------------------------
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// Initialization Overview:
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//
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// Initialize x6 as a virtual pointer to the test results
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// Initialize x16 as a physical pointer to the test results
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// Set up stack pointer (sp = x2)
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// Set up the exception Handler, keeping the original handler in x4.
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//
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// ---------------------------------------------------------------------------------------------
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// address for test results
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la x6, test_1_res
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la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
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// any time either is used, both must be updated.
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// address for stack
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la sp, top_of_stack
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// trap handler setup
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la x1, machine_trap_handler
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csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
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li a0, 0
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li a1, 0
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li a2, 0 // reset trap handler inputs to zero
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// go to first test!
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j begin_test
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// ---------------------------------------------------------------------------------------------
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// General traps Handler
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//
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// Handles traps by branching to different behaviors based on mcause.
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//
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// Note that allowing the exception handler to change mode for a program is a huge security
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// hole, but this is an expedient way of writing tests that need different modes
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//
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// input parameters:
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//
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// a0 (x10):
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// 0: halt program with no failures
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// 1: halt program with failure in x11 = a1
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// 2: go to machine mode
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// 3: go to supervisor mode
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// 4: go to user mode
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// others: do nothing
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//
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// a1 (x11):
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// VPN for return address after changing privilege mode.
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// This should be the base VPN with no offset.
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// 0x0 : defaults to next instruction on the same page the trap was called on.
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//
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// a2 (x12):
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// Pagetype of the current address VPN before changing privilge mode
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// Used so that we can know how many bits of the adress are the offset.
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// Ignored if a1 == 0x0
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// 0: Kilopage
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// 1: Megapage
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// 2: Gigapage
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// 3: Terapage
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//
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// --------------------------------------------------------------------------------------------
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machine_trap_handler:
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// The processor is always in machine mode when a trap takes us here
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// save registers on stack before using
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sd x1, -8(sp)
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sd x5, -16(sp)
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// Record trap
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csrr x1, mcause // record the mcause
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sd x1, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8 // update pointers for logging results
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// Respond to trap based on cause
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// All interrupts should return after being logged
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, trapreturn // return from interrupt
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// Other trap handling is specified in the vector Table
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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la x5, trap_handler_vector_table
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add x5, x5, x1 // compute address of vector in Table
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ld x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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segfault:
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ld x5, -16(sp) // restore registers from stack before faulting
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ld x1, -8(sp)
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j terminate_test // halt program.
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trapreturn:
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// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
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csrr x1, mepc // get the mepc
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addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
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// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
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// ******** but in the handler, we work in M mode with physical addresses
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// This means the address in mepc is suddenly pointing somewhere else.
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// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
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// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
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// lw x5, 0(x1) // read the faulting instruction
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// li x1, 3 // check bottom 2 bits of instruction to see if compressed
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// and x5, x5, x1 // mask the other bits
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// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
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// trapreturn_compressed:
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 2 // add 2 to find the next instruction
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// j trapreturn_specified // and return
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// trapreturn_uncompressed:
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 4 // add 4 to find the next instruction
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trapreturn_specified:
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// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
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// so that when we return to a new virtual address, they're all in the right spot as well.
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beqz a1, trapreturn_finished // either update values, of go to default return address.
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la x5, trap_return_pagetype_table
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slli a2, a2, 3
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add x5, x5, a2
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ld a2, 0(x5) // a2 = number of offset bits in current page type
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li x5, 1
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sll x5, x5, a2
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addi x5, x5, -1 // x5 = mask bits for offset into current pagetype
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// reset the top of the stack, x1
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ld x7, -8(sp)
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and x7, x5, x7 // x7 = offset for x1
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add x7, x7, a1 // x7 = new address for x1
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sd x7, -8(sp)
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// reset the second spot in the stack, x5
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ld x7, -16(sp)
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and x7, x5, x7 // x7 = offset for x5
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add x7, x7, a1 // x7 = new address for x5
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sd x7, -16(sp)
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// reset x6, the pointer for the virtual address of the output of the tests
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and x7, x5, x6 // x7 = offset for x6
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add x6, x7, a1 // x6 = new address for the result pointer
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// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
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and x1, x5, x1 // x1 = offset for the return address
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add x1, x1, a1 // x1 = new return address.
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li a1, 0
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li a2, 0 // reset trapreturn inputs to the trap handler
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trapreturn_finished:
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csrw mepc, x1 // update the mepc with address of next instruction
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ld x5, -16(sp) // restore registers from stack before returning
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ld x1, -8(sp)
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mret // return from trap
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ecallhandler:
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// Check input parameter a0. encoding above.
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// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
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li x5, 2 // case 2: change to machine mode
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beq a0, x5, ecallhandler_changetomachinemode
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li x5, 3 // case 3: change to supervisor mode
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beq a0, x5, ecallhandler_changetosupervisormode
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li x5, 4 // case 4: change to user mode
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beq a0, x5, ecallhandler_changetousermode
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// unsupported ecalls should segfault
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j segfault
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ecallhandler_changetomachinemode:
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// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
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li x1, 0b1100000000000
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csrs mstatus, x1
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j trapreturn
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ecallhandler_changetosupervisormode:
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// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
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li x1, 0b1100000000000
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csrc mstatus, x1
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li x1, 0b0100000000000
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csrs mstatus, x1
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j trapreturn
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ecallhandler_changetousermode:
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// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
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li x1, 0b1100000000000
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csrc mstatus, x1
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j trapreturn
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instrfault:
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
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j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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illegalinstr:
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j trapreturn // return to the code after recording the mcause
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accessfault:
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// *** What do I have to do here?
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j trapreturn
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// Table of trap behavior
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// lists what to do on each exception (not interrupts)
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// unexpected exceptions should cause segfaults for easy detection
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// Expected exceptions should increment the EPC to the next instruction and return
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.align 3 // aligns this data table to an 8 byte boundary
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trap_handler_vector_table:
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.8byte segfault // 0: instruction address misaligned
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.8byte instrfault // 1: instruction access fault
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.8byte illegalinstr // 2: illegal instruction
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.8byte segfault // 3: breakpoint
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.8byte segfault // 4: load address misaligned
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.8byte accessfault // 5: load access fault
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.8byte segfault // 6: store address misaligned
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.8byte accessfault // 7: store access fault
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.8byte ecallhandler // 8: ecall from U-mode
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.8byte ecallhandler // 9: ecall from S-mode
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.8byte segfault // 10: reserved
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.8byte ecallhandler // 11: ecall from M-mode
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.8byte instrfault // 12: instruction page fault
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.8byte trapreturn // 13: load page fault
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.8byte segfault // 14: reserved
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.8byte trapreturn // 15: store page fault
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.align 3
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trap_return_pagetype_table:
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.8byte 0xC // 0: kilopage has 12 offset bits
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.8byte 0x15 // 1: megapage has 21 offset bits
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.8byte 0x1E // 2: gigapage has 30 offset bits
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.8byte 0x27 // 3: terapage has 39 offset bits
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begin_test: // label here to jump to so we dont go through the trap handler before starting the test
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.endm // Ends the initialization macro that set up the begginnning of the tests and the trap handler.
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// Test Summary table!
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// Test Name : Description : Fault output value : Normal output values
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// ---------------------:-------------------------------------------:-------------------------------:------------------------------------------------------
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// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
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// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
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// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
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// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
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// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
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// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
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// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_baremetal : satp.MODE = bare metal : None : None
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// goto_sv39 : satp.MODE = sv39 : None : None
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// goto_sv48 : satp.MODE = sv48 : None : None
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// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
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// write_csr : write to specified CSR : CSR value before test attempt : value written to CSR
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// read_csr : read from specified CSR : *** None? Mcause or fault? : value read back from CSR
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// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value
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.macro write64_test ADDR VAL
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// attempt to write VAL to ADDR
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// Success outputs:
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// None
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// Fault outputs:
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// 0x6: misaligned address
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// 0x7: access fault
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// 0xf: page fault
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li x29, \VAL
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li x30, \ADDR
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sd x29, 0(x30)
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.endm
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.macro write32_test ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sw x29, 0(x30)
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.endm
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.macro write16_test ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sh x29, 0(x30)
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.endm
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.macro write08_test ADDR VAL
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// all write tests have the same description/outputs as write64
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li x29, \VAL
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li x30, \ADDR
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sb x29, 0(x30)
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.endm
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.macro read64_test ADDR
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// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
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// Success outputs:
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// value read out from ADDR
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// Fault outputs:
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// One of the following followed by 0xBAD
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// 0x4: misaligned address
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// 0x5: access fault
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// 0xD: page fault
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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ld x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro read32_test ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lw x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro read16_test ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lh x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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.macro read08_test ADDR
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// All reads have the same description/outputs as read64.
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// They will store the sign extended value of what was read out at ADDR
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li x7, 0xBAD // bad value that will be overwritten on good reads.
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li x29, \ADDR
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lb x7, 0(x29)
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sd x7, 0(x6)
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addi x6, x6, 8
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addi x16, x16, 8
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.endm
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// These goto_x_mode tests all involve invoking the trap handler,
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// So their outputs are inevitably:
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// 0x8: test called from U mode
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// 0x9: test called from S mode
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// 0xB: test called from M mode
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// they generally do not fault or cause issues as long as these modes are enabled
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// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
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.macro goto_m_mode RETURN_VPN RETURN_PAGETYPE
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li a0, 2 // determine trap handler behavior (go to supervisor mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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.macro goto_s_mode RETURN_VPN RETURN_PAGETYPE
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li a0, 3 // determine trap handler behavior (go to supervisor mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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.macro goto_u_mode RETURN_VPN RETURN_PAGETYPE
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li a0, 4 // determine trap handler behavior (go to supervisor mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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ecall // writes mcause to the output.
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// now in S mode
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.endm
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// These tests change virtual memory settings, turning it on/off and changing between types.
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// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
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.macro goto_baremetal
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// Turn translation off
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li x7, 0 // satp.MODE value for bare metal (0)
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slli x7, x7, 60
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||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro goto_sv39
|
||||
// Turn on sv39 virtual memory
|
||||
li x7, 8 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro goto_sv48
|
||||
// Turn on sv48 virtual memory
|
||||
li x7, 9 // satp.MODE value for Sv39 (8)
|
||||
slli x7, x7, 60
|
||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro write_csr CSR VAL
|
||||
// attempt to write CSR with VAL *** ASSUMES RW access to CSR in whatever privilege mode is running
|
||||
// Success outputs:
|
||||
// value read back out from CSR after writing
|
||||
// Fault outputs:
|
||||
// The previous CSR value before write attempt
|
||||
// *** Is there an associated mstatus? maybe 0x2???
|
||||
li x29, \VAL
|
||||
csrw \CSR\(), x29
|
||||
csrr x30, \CSR
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro csr_r_access CSR
|
||||
// verify that a csr is accessible to read but not to write
|
||||
// Success outputs:
|
||||
// 0x11 *** consider changing to something more meaningful
|
||||
// Fault outputs:
|
||||
// 0x2, then
|
||||
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
|
||||
csrr x29, \CSR
|
||||
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
||||
csrr x30, \CSR
|
||||
bne x30, x29, 1f // 1f represents r_access_success
|
||||
li x30, 0xBAD // Write succeeded, violating read only permissions.
|
||||
j 2f // j r_access_end
|
||||
1: // r_access_success
|
||||
li x30, 0x11
|
||||
2: // r_access end
|
||||
sd x30, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro execute_at_address ADDR
|
||||
// Execute the code already written to ADDR, returning the value in x7.
|
||||
// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
|
||||
// Assumes the code modifies x7, usually to become 0x111.
|
||||
// Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret)
|
||||
// Success outputs:
|
||||
// modified value of x7. (0x111 if you use the sample code)
|
||||
// Fault outputs:
|
||||
// One of the following followed by 0xBAD
|
||||
// 0x0: misaligned address
|
||||
// 0x1: access fault
|
||||
// 0xC: page fault
|
||||
fence.i // forces caches and main memory to sync so execution code written to ADDR can run.
|
||||
li x7, 0xBAD
|
||||
li x28, \ADDR
|
||||
jalr x28 // jump to executable test code
|
||||
sd x7, 0(x6)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
.macro END_TESTS
|
||||
// invokes one final ecall to return to machine mode then terminates this program, so the output is
|
||||
// 0x8: termination called from U mode
|
||||
// 0x9: termination called from S mode
|
||||
// 0xB: termination called from M mode
|
||||
|
||||
terminate_test:
|
||||
|
||||
li a0, 2 // Trap handler behavior (go to machine mode)
|
||||
ecall // writes mcause to the output.
|
||||
csrw mtvec, x4 // restore original trap handler to halt program
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
RVTEST_DATA_END
|
||||
|
||||
.align 3 // align stack to 8 byte boundary
|
||||
bottom_of_stack:
|
||||
.fill 1024, 4, 0xdeadbeef
|
||||
top_of_stack:
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
test_1_res:
|
||||
.fill 1024, 4, 0xdeadbeef
|
||||
|
||||
RVMODEL_DATA_END
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
.endm // ends the macro that terminates this test program.
|
||||
Loading…
Reference in New Issue
Block a user