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start migrating busybear over to InstrRawD/PCD

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this breaks busybear for now
This commit is contained in:
Noah Boorstin 2021-03-22 23:45:02 -04:00
parent 1592332d41
commit 3c131bb2bd
2 changed files with 47 additions and 47 deletions
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8
wally-pipelined/regression/wally-busybear.do
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@ -45,13 +45,13 @@ add wave /testbench_busybear/reset
add wave -divider add wave -divider
add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/PCtext
add wave -hex /testbench_busybear/pcExpected add wave -hex /testbench_busybear/pcExpected
add wave -hex /testbench_busybear/dut/hart/ifu/PCF add wave -hex /testbench_busybear/dut/hart/ifu/PCD
add wave -hex /testbench_busybear/dut/hart/ifu/ic/InstrF add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
add wave -hex /testbench_busybear/dut/hart/ifu/StallD add wave -hex /testbench_busybear/dut/hart/ifu/StallD
add wave -hex /testbench_busybear/dut/hart/ifu/FlushD add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
add wave /testbench_busybear/CheckInstrF add wave /testbench_busybear/CheckInstrD
add wave /testbench_busybear/lastCheckInstrF add wave /testbench_busybear/lastCheckInstrD
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
add wave -divider add wave -divider

86
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -7,7 +7,7 @@ module testbench_busybear();
logic [31:0] GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsOut, GPIOPinsEn;
// instantiate device to be tested // instantiate device to be tested
logic [31:0] CheckInstrF; logic [31:0] CheckInstrD;
logic [`AHBW-1:0] HRDATA; logic [`AHBW-1:0] HRDATA;
logic [31:0] HADDR; logic [31:0] HADDR;
@ -344,7 +344,7 @@ module testbench_busybear();
initial begin initial begin
speculative = 0; speculative = 0;
end end
logic [63:0] lastCheckInstrF, lastPC, lastPC2; logic [63:0] lastCheckInstrD, lastPC, lastPC2;
string PCtextW, PCtext2W; string PCtextW, PCtext2W;
logic [31:0] InstrWExpected; logic [31:0] InstrWExpected;
@ -379,36 +379,36 @@ module testbench_busybear();
end end
logic [31:0] InstrMask; logic [31:0] InstrMask;
logic forcedInstr; logic forcedInstr;
logic [63:0] lastPCF; logic [63:0] lastPCD;
always @(dut.PCF or dut.hart.ifu.ic.InstrF or reset) begin always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset) begin
if(~HWRITE) begin if(~HWRITE) begin
#3; #3;
if (~reset && dut.hart.ifu.ic.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
if (dut.PCF !== lastPCF) begin if (dut.hart.ifu.PCD !== lastPCD) begin
lastCheckInstrF = CheckInstrF; lastCheckInstrD = CheckInstrD;
lastPC <= dut.PCF; lastPC <= dut.hart.ifu.PCD;
lastPC2 <= lastPC; lastPC2 <= lastPC;
if (speculative && (lastPC != pcExpected)) begin if (speculative && (lastPC != pcExpected)) begin
speculative = ~equal(dut.PCF,pcExpected,3); speculative = ~equal(dut.hart.ifu.PCD,pcExpected,3);
if(dut.PCF===pcExpected) begin if(dut.hart.ifu.PCD===pcExpected) begin
if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
force CheckInstrF = 32'b0010011; force CheckInstrD = 32'b0010011;
release CheckInstrF; release CheckInstrD;
force dut.hart.ifu.ic.InstrF = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011;
#7; #7;
release dut.hart.ifu.ic.InstrF; release dut.hart.ifu.InstrRawD;
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
else begin else begin
if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD if(dut.hart.ifu.InstrRawD[28:27] != 2'b11 && dut.hart.ifu.InstrRawD[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; force CheckInstrD = {12'b0, CheckInstrD[19:7], 7'b0000011};
release CheckInstrF; release CheckInstrD;
force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011}; force dut.hart.ifu.InstrRawD = {12'b0, dut.hart.ifu.InstrRawD[19:7], 7'b0000011};
#7; #7;
release dut.hart.ifu.ic.InstrF; release dut.hart.ifu.InstrRawD;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.hart.ifu.PCD);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
@ -428,26 +428,26 @@ module testbench_busybear();
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
PCtext = {PCtext, " ", PCtext2}; PCtext = {PCtext, " ", PCtext2};
end end
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
if(dut.PCF === pcExpected) begin if(dut.hart.ifu.PCD === pcExpected) begin
if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
force CheckInstrF = 32'b0010011; force CheckInstrD = 32'b0010011;
release CheckInstrF; release CheckInstrD;
force dut.hart.ifu.ic.InstrF = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011;
#7; #7;
release dut.hart.ifu.ic.InstrF; release dut.hart.ifu.InstrRawD;
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
else begin else begin
if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD if(dut.hart.ifu.InstrRawD[28:27] != 2'b11 && dut.hart.ifu.InstrRawD[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; force CheckInstrD = {12'b0, CheckInstrD[19:7], 7'b0000011};
release CheckInstrF; release CheckInstrD;
force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011}; force dut.hart.ifu.InstrRawD = {12'b0, dut.hart.ifu.InstrRawD[19:7], 7'b0000011};
#7; #7;
release dut.hart.ifu.ic.InstrF; release dut.hart.ifu.InstrRawD;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.hart.ifu.PCD);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
@ -465,7 +465,7 @@ module testbench_busybear();
end end
instrs += 1; instrs += 1;
// are we at a branch/jump? // are we at a branch/jump?
casex (lastCheckInstrF[31:0]) casex (lastCheckInstrD[31:0])
32'b00000000001000000000000001110011, // URET 32'b00000000001000000000000001110011, // URET
32'b00010000001000000000000001110011, // SRET 32'b00010000001000000000000001110011, // SRET
32'b00110000001000000000000001110011, // MRET 32'b00110000001000000000000001110011, // MRET
@ -486,18 +486,18 @@ module testbench_busybear();
endcase endcase
//check things! //check things!
if ((~speculative) && (~equal(dut.PCF,pcExpected,3))) begin if ((~speculative) && (~equal(dut.hart.ifu.PCD,pcExpected,3))) begin
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.PCF, pcExpected); $display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, pcExpected);
`ERROR `ERROR
end end
InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF; InstrMask = CheckInstrD[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.ic.InstrF) !== (InstrMask & CheckInstrF))) begin if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrRawD) !== (InstrMask & CheckInstrD))) begin
$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.ic.InstrF, CheckInstrF, dut.PCF); $display("%0t ps, instr %0d: InstrD does not equal CheckInstrD: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrRawD, CheckInstrD, dut.hart.ifu.PCD);
`ERROR `ERROR
end end
end end
end end
lastPCF = dut.PCF; lastPCD = dut.hart.ifu.PCD;
end end
end end
end end