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Fixed fpga to work with the updated regression changes.

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Rose Thompson 2024-04-22 10:42:01 -05:00
parent e467e46967
commit 3bed733301
1 changed files with 2 additions and 1 deletions
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fpga/generator/Makefile
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@ -57,7 +57,8 @@ PreProcessFiles:
# modify config *** RT: eventually setup for variably defined sized memory # modify config *** RT: eventually setup for variably defined sized memory
#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh #sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA # This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
$(dst)/%.log: %.tcl $(dst)/%.log: %.tcl
mkdir -p IP mkdir -p IP