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Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.

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Remove preload from dtim.
This commit is contained in:
Ross Thompson 2021-12-08 15:50:15 -06:00
parent 37451b8978
commit 3bdda9687a
3 changed files with 2 additions and 2 deletions
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0
wally-pipelined/src/sdc/counter.sv → wally-pipelined/src/sdc/SDCcounter.sv
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2
wally-pipelined/src/uncore/dtim.sv
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@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( module dtim #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSELTim, input logic HSELTim,
input logic [31:0] HADDR, input logic [31:0] HADDR,

2
wally-pipelined/src/uncore/uncore.sv
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@ -103,7 +103,7 @@ module uncore (
end end
if (`BOOTTIM_SUPPORTED) begin : bootdtim if (`BOOTTIM_SUPPORTED) begin : bootdtim
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE), .PRELOAD("blink-led.mem")) dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE))
bootdtim( bootdtim(
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELTim(HSELBootTim), .HADDR, .HSELTim(HSELBootTim), .HADDR,