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Update some spacing to make it look better

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James Stine 2023-06-05 11:03:06 -05:00
parent f526519573
commit 3bd5bbce48
1 changed files with 24 additions and 31 deletions
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7
src/fpu/fcvt.sv
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@ -65,7 +65,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
// seperate OpCtrl for code readability // seperate OpCtrl for code readability
assign Signed = OpCtrl[0]; assign Signed = OpCtrl[0];
assign Int64 = OpCtrl[1]; assign Int64 = OpCtrl[1];
@ -79,7 +78,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else if (P.FPSIZES == 3 | P.FPSIZES == 4) else if (P.FPSIZES == 3 | P.FPSIZES == 4)
assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0]; assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0];
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// negation // negation
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
@ -143,7 +141,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
end end
// select the old exponent // select the old exponent
// int -> fp : largest bias + XLEN-1 // int -> fp : largest bias + XLEN-1
// fp -> ??? : XExp // fp -> ??? : XExp
@ -185,13 +182,11 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// oldexp - biasold - LeadingZeros + newbias // oldexp - biasold - LeadingZeros + newbias
assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias}; assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
// find if the result is dnormal or underflows // find if the result is dnormal or underflows
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
// - can't underflow an integer to Fp conversion // - can't underflow an integer to Fp conversion
assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp; assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// shifter // shifter
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
@ -213,7 +208,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
else ShiftAmt = LeadingZeros; else ShiftAmt = LeadingZeros;
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// sign // sign
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
@ -230,4 +224,3 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else Cs = Xs; else Cs = Xs;
endmodule endmodule