From 3bcb42adb6334db9c4a81daab23383613478d413 Mon Sep 17 00:00:00 2001 From: Alessandro Maiuolo Date: Sun, 18 Dec 2022 19:04:36 -0800 Subject: [PATCH] fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) --- pipelined/config/shared/wally-shared.vh | 6 +++--- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 6 +++--- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 8 ++++---- 6 files changed, 15 insertions(+), 15 deletions(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index ee09a4260..2c53d1e41 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -109,8 +109,8 @@ `define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6)) // division constants -`define RADIX 32'h4 -`define DIVCOPIES 32'h2 +`define RADIX 32'h2 +`define DIVCOPIES 32'h1 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3) // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input `define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input @@ -120,7 +120,7 @@ `define LOGR ((`RADIX==2) ? 32'h1 : 32'h2) `define RK (`DIVCOPIES*`LOGR) // r*k used for intdiv preproc `define LOGK ($clog2(`DIVCOPIES)) -`define LOGRK ($clog2(`RK)) +`define LOGRK ($clog2(`RADIX*`DIVCOPIES)) // log2(R*k) // FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES)) // one iteration is required for the integer bit for minimally redundent radix-4 `define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 8b9b84993..ffafb3662 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -114,13 +114,13 @@ module fdivsqrtiter( generate for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations if (`RADIX == 2) begin: stage - fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwap, + fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwap, .MDUE, .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end else begin: stage logic j1; assign j1 = (i == 0 & ~C[0][`DIVb-1]); - fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwap, + fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwap, .MDUE, .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index e80298d67..2e493450e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -66,7 +66,7 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] WCF, WSF; assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1)); - assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}}; + assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0}; csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero}; aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0); assign WZeroM = weq0|(wfeq0 & Firstun); diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index b7bcf949b..a54b20ab4 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -34,7 +34,7 @@ module fdivsqrtqsel4cmp ( input logic [2:0] Dmsbs, input logic [4:0] Smsbs, input logic [7:0] WSmsbs, WCmsbs, - input logic Sqrt, j1, OTFCSwap, + input logic SqrtE, j1, OTFCSwap, MDUE, output logic [3:0] udigit ); logic [6:0] Wmsbs; @@ -72,7 +72,7 @@ module fdivsqrtqsel4cmp ( // Choose A for current operation always_comb - if (Sqrt) begin + if (SqrtE & ~MDUE) begin if (j1) A = 3'b101; else if (Smsbs == 5'b10000) A = 3'b111; else A = Smsbs[2:0]; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 088aff3a7..6866160f6 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -38,7 +38,7 @@ module fdivsqrtstage2 ( input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, input logic SqrtE, - input logic OTFCSwap, + input logic OTFCSwap, MDUE, output logic un, output logic [`DIVb+1:0] CNext, output logic [`DIVb:0] UNext, UMNext, @@ -73,8 +73,8 @@ module fdivsqrtstage2 ( // Partial Product Generation // WSA, WCA = WS + WC - qD - assign AddIn = SqrtE ? F : Dsel; - csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA); + assign AddIn = (SqrtE & ~MDUE) ? F : Dsel; + csa #(`DIVb+4) csa(WS, WC, AddIn, up&~(SqrtE & ~MDUE), WSA, WCA); assign WSNext = WSA << 1; assign WCNext = WCA << 1; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index f006b0478..105e71f80 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -36,7 +36,7 @@ module fdivsqrtstage4 ( input logic [`DIVb:0] U, UM, input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, - input logic SqrtE, j1, OTFCSwap, + input logic SqrtE, j1, OTFCSwap, MDUE, output logic [`DIVb+1:0] CNext, output logic un, output logic [`DIVb:0] UNext, UMNext, @@ -65,7 +65,7 @@ module fdivsqrtstage4 ( assign WCmsbs = WC[`DIVb+3:`DIVb-4]; assign WSmsbs = WS[`DIVb+3:`DIVb-4]; - fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .Sqrt(SqrtE), .j1, .udigit, .OTFCSwap); + fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwap, .MDUE); assign un = 1'b0; // unused for radix 4 // F generation logic @@ -84,8 +84,8 @@ module fdivsqrtstage4 ( // Residual Update // {WS, WC}}Next = (WS + WC - qD or F) << 2 - assign AddIn = SqrtE ? F : Dsel; - assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D + assign AddIn = (SqrtE & ~MDUE) ? F : Dsel; + assign CarryIn = ~(SqrtE & ~MDUE) & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA); assign WSNext = WSA << 2; assign WCNext = WCA << 2;