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renamed BusBuffer to FetchBuffer

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This commit is contained in:
David Harris 2022-08-25 10:44:39 -07:00
parent dda3b441d7
commit 3ba961d1a8
5 changed files with 17 additions and 20 deletions
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9
pipelined/src/cache/cache.sv vendored
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@ -58,7 +58,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic CacheBusAck,
input logic SelLSUBusWord,
input logic [LOGBWPL-1:0] WordCount,
input logic [LINELEN-1:0] LSUBusBuffer,
input logic [LINELEN-1:0] FetchBuffer,
output logic [`PA_BITS-1:0] CacheBusAdr,
output logic [WORDLEN-1:0] ReadDataWord);
@ -150,7 +150,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
.y(WordOffsetAddr));
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, LSUBusBuffer, SelBusBuffer, ReadDataLine);
mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelBusBuffer, ReadDataLine);
subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
.PAdr(WordOffsetAddr),
@ -173,10 +173,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
for(index = 0; index < LINELEN/8; index++) begin
mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]),
.d1(LSUBusBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index]));
.d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index]));
end
//mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
// .d1(LSUBusBuffer), .s(SetValid), .y(CacheWriteData));
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}),

6
pipelined/src/ebu/ahblite.sv
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@ -83,7 +83,6 @@ module ahblite (
statetype BusState, NextBusState;
logic LSUGrant;
logic [31:0] AccessAddress;
assign HCLK = clk;
assign HRESETn = ~reset;
@ -128,10 +127,9 @@ module ahblite (
endcase
// bus outputs
// LSU/IFU mux: choose source of access
assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
assign AccessAddress = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
assign HADDR = AccessAddress;
assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.

8
pipelined/src/ifu/ifu.sv
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@ -196,7 +196,7 @@ module ifu (
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
logic [LINELEN-1:0] ILSUBusBuffer;
logic [LINELEN-1:0] FetchBuffer;
logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
logic SelUncachedAdr;
@ -209,13 +209,13 @@ module ifu (
.WordCount(),
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
.DLSUBusBuffer(ILSUBusBuffer), .LSUPAdrM(PCPF),
.FetchBuffer, .LSUPAdrM(PCPF),
.SelUncachedAdr,
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM());
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ILSUBusBuffer[32-1:0]),
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
.s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
@ -224,7 +224,7 @@ module ifu (
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM,
.LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(), .ReadDataWord(FinalInstrRawF),

6
pipelined/src/lsu/busdp.sv
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@ -46,7 +46,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
output logic BusRead,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [1:0] HTRANS, // For AHBLite
output logic [1:0] HTRANS,
output logic BusTransComplete,
output logic [`PA_BITS-1:0] HADDR,
output logic [LOGWPL-1:0] WordCount,
@ -56,7 +56,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
input logic CacheFetchLine,
input logic CacheWriteLine,
output logic CacheBusAck,
output logic [LINELEN-1:0] DLSUBusBuffer, //*** change name.
output logic [LINELEN-1:0] FetchBuffer,
output logic SelUncachedAdr,
// lsu/ifu interface
@ -80,7 +80,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
logic [WORDSPERLINE-1:0] CaptureWord;
assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed);
flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA),
.q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN]));
.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
end
mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR);
assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;

8
pipelined/src/lsu/lsu.sv
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@ -215,7 +215,7 @@ module lsu (
localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;
logic [LINELEN-1:0] DLSUBusBuffer;
logic [LINELEN-1:0] FetchBuffer;
logic [`PA_BITS-1:0] DCacheBusAdr;
logic DCacheWriteLine;
logic DCacheFetchLine;
@ -228,11 +228,11 @@ module lsu (
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.WordCount, .SelLSUBusWord,
.LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM,
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .LSUPAdrM,
.SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM);
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}),
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
.s(SelUncachedAdr), .y(LSUHWDATA));
@ -246,7 +246,7 @@ module lsu (
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
.LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine),
.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
end else begin : passthrough