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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Possible fixes for earily messup of rv32ic and rv64ic configs.
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@ -49,11 +49,11 @@
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`define UARCH_SUPERSCALR 0
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define UARCH_SINGLECYCLE 0
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// LSU microarchitectural Features
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// LSU microarchitectural Features
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`define DMEM 0
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`define DMEM 1
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`define IROM 0
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`define IROM 1
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`define BUS 0
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`define BUS 0
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`define DCACHE 1
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`define DCACHE 0
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`define ICACHE 1
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`define ICACHE 0
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`define VIRTMEM_SUPPORTED 0
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`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define BIGENDIAN_SUPPORTED 0
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`define BIGENDIAN_SUPPORTED 0
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@ -56,7 +56,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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exec ./slack-notifier/slack-notifier.py
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exec ./slack-notifier/slack-notifier.py
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} else {
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} else {
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
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@ -223,7 +223,7 @@ logic [3:0] dummy;
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else pathname = tvpaths[1]; */
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else pathname = tvpaths[1]; */
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (TEST == "fpga") begin
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if (`FPGA) begin
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string romfilename, sdcfilename;
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string romfilename, sdcfilename;
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romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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