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Possible fixes for earily messup of rv32ic and rv64ic configs.

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This commit is contained in:
Ross Thompson 2022-08-25 14:42:08 -05:00
parent f67010c688
commit 3b612d6201
3 changed files with 6 additions and 6 deletions
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8
pipelined/config/rv32ic/wally-config.vh
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@ -49,11 +49,11 @@
`define UARCH_SUPERSCALR 0 `define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define DMEM 0 `define DMEM 1
`define IROM 0 `define IROM 1
`define BUS 0 `define BUS 0
`define DCACHE 1 `define DCACHE 0
`define ICACHE 1 `define ICACHE 0
`define VIRTMEM_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0 `define BIGENDIAN_SUPPORTED 0

2
pipelined/regression/wally-pipelined-batch.do
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@ -56,7 +56,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
exec ./slack-notifier/slack-notifier.py exec ./slack-notifier/slack-notifier.py
} else { } else {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt

2
pipelined/testbench/testbench.sv
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@ -223,7 +223,7 @@ logic [3:0] dummy;
else pathname = tvpaths[1]; */ else pathname = tvpaths[1]; */
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"};
if (TEST == "fpga") begin if (`FPGA) begin
string romfilename, sdcfilename; string romfilename, sdcfilename;
romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"};