From 3b5627b7531bf5600defa44f2df8f00dd7e47888 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 8 Jun 2021 14:56:00 -0400 Subject: [PATCH] reverted to working version with new mmu comments --- wally-pipelined/src/dmem/dmem.sv | 4 ++-- wally-pipelined/src/ifu/ifu.sv | 4 ++-- wally-pipelined/src/{uncore => mmu}/adrdec.sv | 0 wally-pipelined/src/mmu/camline.sv | 11 +++-------- wally-pipelined/src/mmu/mmu.sv | 6 +++--- wally-pipelined/src/mmu/pmachecker.sv | 8 ++++---- wally-pipelined/src/mmu/pmpchecker.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 6 +++--- wally-pipelined/src/mmu/tlbcam.sv | 6 +++--- wally-pipelined/src/mmu/tlbram.sv | 6 +++--- 10 files changed, 24 insertions(+), 29 deletions(-) rename wally-pipelined/src/{uncore => mmu}/adrdec.sv (100%) diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 08ada496d..985a47514 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -71,7 +71,7 @@ module dmem ( input logic HWRITE, input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage. input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. @@ -96,7 +96,7 @@ module dmem ( // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), - .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM), + .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index b9ccec751..4518ada0a 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -80,7 +80,7 @@ module ifu ( input logic HWRITE, input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage. input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF, output logic ISquashBusAccessF, @@ -105,7 +105,7 @@ module ifu ( // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), - .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), + .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), diff --git a/wally-pipelined/src/uncore/adrdec.sv b/wally-pipelined/src/mmu/adrdec.sv similarity index 100% rename from wally-pipelined/src/uncore/adrdec.sv rename to wally-pipelined/src/mmu/adrdec.sv diff --git a/wally-pipelined/src/mmu/camline.sv b/wally-pipelined/src/mmu/camline.sv index 7c22582a7..6e3f705c3 100644 --- a/wally-pipelined/src/mmu/camline.sv +++ b/wally-pipelined/src/mmu/camline.sv @@ -33,14 +33,14 @@ module camline #(parameter KEY_BITS = 20, input logic clk, reset, // input to check which SvMode is running - input logic [`SVMODE_BITS-1:0] SvMode, +// input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed. // The requested page number to compare against the key input logic [KEY_BITS-1:0] VirtualPageNumber, // Signals to write a new entry to this line input logic CAMLineWrite, - input logic [1:0] PageTypeWrite, + input logic [1:0] PageTypeWriteVal, // Flush this line (set valid to 0) input logic TLBFlush, @@ -96,13 +96,8 @@ module camline #(parameter KEY_BITS = 20, end endgenerate - // When determining a match for a superpage, we might use only a portion of - // the input VirtualPageNumber. Unused parts of the VirtualPageNumber are - // zeroed in VirtualPageNumberQuery to better match with Key. - logic [KEY_BITS-1:0] VirtualPageNumberQuery; - // On a write, update the type of the page referred to by this line. - flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWrite, PageType); + flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType); //mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType); // On a write, set the valid bit high and update the stored key. diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index b8db572d4..32c50f871 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -49,8 +49,8 @@ module mmu #(parameter ENTRY_BITS = 3, input logic [`XLEN-1:0] VirtualAddress, // Controls for writing a new entry to the TLB - input logic [`XLEN-1:0] PageTableEntryWrite, - input logic [1:0] PageTypeWrite, + input logic [`XLEN-1:0] PTEWriteVal, + input logic [1:0] PageTypeWriteVal, input logic TLBWrite, // Invalidate all TLB entries @@ -70,7 +70,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic HWRITE, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. output logic SquashBusAccess, // *** send to privileged unit output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM, diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index db4c648b2..61c02426c 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -28,13 +28,13 @@ `include "wally-config.vh" module pmachecker ( - input logic clk, reset, +// input logic clk, reset, // *** unused in this module and all sub modules. input logic [31:0] HADDR, input logic [2:0] HSIZE, - input logic [2:0] HBURST, +// input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused. - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use. output logic Cacheable, Idempotent, AtomicAllowed, output logic PMASquashBusAccess, @@ -92,7 +92,7 @@ module pmachecker ( endmodule module attributes ( - input logic clk, reset, +// input logic clk, reset, // *** unused in this module and all sub modules. input logic [31:0] Address, diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 56739aa34..62df15801 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module pmpchecker ( - input logic clk, reset, +// input logic clk, reset, //*** it seems like clk, reset is also not needed here? input logic [31:0] HADDR, diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index c06e02f6f..e4e2060c5 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -70,8 +70,8 @@ module tlb #(parameter ENTRY_BITS = 3, input logic [`XLEN-1:0] VirtualAddress, // Controls for writing a new entry to the TLB - input logic [`XLEN-1:0] PageTableEntryWrite, - input logic [1:0] PageTypeWrite, + input logic [`XLEN-1:0] PTEWriteVal, + input logic [1:0] PageTypeWriteVal, input logic TLBWrite, // Invalidate all TLB entries @@ -119,7 +119,7 @@ module tlb #(parameter ENTRY_BITS = 3, assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; // Decode the integer encoded WriteIndex into the one-hot encoded WriteLines - decoder writedecoder(WriteIndex, WriteLines); + decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines); // The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64 // this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower, diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index a37f893c5..cf66951f7 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -33,8 +33,8 @@ module tlbcam #(parameter ENTRY_BITS = 3, parameter SEGMENT_BITS = 10) ( input logic clk, reset, input logic [KEY_BITS-1:0] VirtualPageNumber, - input logic [1:0] PageTypeWrite, - input logic [`SVMODE_BITS-1:0] SvMode, + input logic [1:0] PageTypeWriteVal, +// input logic [`SVMODE_BITS-1:0] SvMode, // *** may not need to be used. input logic TLBWrite, input logic TLBFlush, input logic [2**ENTRY_BITS-1:0] WriteLines, @@ -69,7 +69,7 @@ module tlbcam #(parameter ENTRY_BITS = 3, // In case there are multiple matches in the CAM, select only one // *** it might be guaranteed that the CAM will never have multiple matches. // If so, this is just an encoder - priorityencoder #(ENTRY_BITS) matchpriority(Matches, VPNIndex); + priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex); assign CAMHit = |Matches & ~TLBFlush; assign HitPageType = PageTypeList[VPNIndex]; diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index f768c7522..9879ce660 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -30,8 +30,8 @@ module tlbram #(parameter ENTRY_BITS = 3) ( input logic clk, reset, input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from - input logic [ENTRY_BITS-1:0] WriteIndex, - input logic [`XLEN-1:0] PageTableEntryWrite, +// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused? + input logic [`XLEN-1:0] PTEWriteVal, input logic TLBWrite, input logic [2**ENTRY_BITS-1:0] WriteLines, @@ -49,7 +49,7 @@ module tlbram #(parameter ENTRY_BITS = 3) ( genvar i; for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite, - PageTableEntryWrite, ram[i]); + PTEWriteVal, ram[i]); end endgenerate