diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv
index 28d15ebbe..42c484393 100644
--- a/pipelined/src/ifu/brpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/brpred/RAsPredictor.sv
@@ -1,13 +1,14 @@
 ///////////////////////////////////////////
 // RASPredictor.sv
 //
-// Written: Ross Thomposn
-// Email: ross1728@gmail.com
-// Created: February 15, 2021
-// Modified: 
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: 15 February 2021
+// Modified: 25 January 2023
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -28,41 +29,42 @@
 
 `include "wally-config.vh"
 
-module RASPredictor
-  #(parameter int StackSize = 16
-    )
-  (input logic              clk,
-   input logic 				reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
-   output logic [`XLEN-1:0] RASPCF,
-   input logic [3:0] 		WrongPredInstrClassD,
-   input logic [3:0] 		InstrClassD, InstrClassE, PredInstrClassF,
-   input logic [`XLEN-1:0] 	PCLinkE
+module RASPredictor #(parameter int StackSize = 16
+)(input  logic             clk,
+  input  logic 			   reset, 
+  input  logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input  logic [3:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
+  input  logic [3:0] 	   InstrClassD, InstrClassE, PredInstrClassF, // Instr class
+  input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a jal
+  output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
    );
 
-  // *** need to repair popped and then flushed returns.
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
   logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
+
   logic 		 PopF;
   logic 		 PushE;
   logic 		 RepairD;
+  logic 		 PossibleRepairD;
   
+  logic 		 DecrementPtr;
   
-
   assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
-  assign RepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE;
+  assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE;
   assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
     
-  assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
+  assign CounterEn = PopF | PushE | RepairD;
 
-  assign PtrD = PopF | RepairD ? PtrM1 : PtrP1;
+  assign DecrementPtr = PopF | PossibleRepairD;
+  mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
-  // *** what happens if jal is executing and there is a return being flushed in Decode?
 
   flopenr #(Depth) PTR(.clk(clk),
       .reset(reset),