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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
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.gitignore
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vendored
@ -24,6 +24,7 @@ testsBP/*/*/*.elf*
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testsBP/*/OBJ/*
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testsBP/*/OBJ/*
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testsBP/*/*.a
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testsBP/*/*.a
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wally-pipelined/linux-testgen/linux-testvectors/*
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wally-pipelined/linux-testgen/linux-testvectors/*
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wally-pipelined/linux-testgen/nohup*
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!wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py
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!wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py
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!wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh
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!wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh
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wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
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wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
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@ -24,4 +24,4 @@
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# =========== Just Do the Thing ==========
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# =========== Just Do the Thing ==========
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# Uncomment this version for the whole thing
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# Uncomment this version for the whole thing
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# - Logs info needed by buildroot testbench
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# - Logs info needed by buildroot testbench
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(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot_new/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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@ -44,7 +44,7 @@ try:
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instrs += 1
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instrs += 1
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storeAMO = ''
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storeAMO = ''
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if instrs % 10000 == 0:
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if instrs % 10000 == 0:
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print(instrs)
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print(instrs,flush=True)
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# Instr in human assembly
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# Instr in human assembly
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wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
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wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
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if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
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if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
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@ -63,6 +63,15 @@ try:
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storeLoc = readLoc
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storeLoc = readLoc
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storeReg = l.split()[-1].split(',')[1]
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storeReg = l.split()[-1].split(',')[1]
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storeAMO = l.split()[-2]
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storeAMO = l.split()[-2]
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if '\tlr' in l:
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currentRead = l.split()[-1].split(',')[0]
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readOffset = "0"
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readLoc = l.split()[-1].split('(')[1][:-1]
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readType = "0" # *** I don't see that readType or lastReadType are ever used; we can probably get rid of them
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if '\tsc' in l:
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storeOffset = "0"
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storeLoc = l.split()[-1].split('(')[1][:-1]
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storeReg = l.split()[-1].split(',')[1]
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if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
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if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
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s = l.split('#')[0].split()[-1]
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s = l.split('#')[0].split()[-1]
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storeReg = s.split(',')[0]
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storeReg = s.split(',')[0]
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