From 39c0d0cdda44b8b56202770278662207cd81abcb Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 11 Mar 2024 01:15:16 -0700 Subject: [PATCH] AES64 simplification --- src/ieu/aes_instructions/aes64d.sv | 2 +- src/ieu/aes_instructions/aes64im.sv | 35 ----------------------------- src/ieu/bmu/bitmanipalu.sv | 14 ++++++------ src/ieu/kmu/zknde64.sv | 4 ++-- 4 files changed, 10 insertions(+), 45 deletions(-) delete mode 100644 src/ieu/aes_instructions/aes64im.sv diff --git a/src/ieu/aes_instructions/aes64d.sv b/src/ieu/aes_instructions/aes64d.sv index 8781988f2..6f6fc172f 100644 --- a/src/ieu/aes_instructions/aes64d.sv +++ b/src/ieu/aes_instructions/aes64d.sv @@ -42,7 +42,7 @@ module aes64d( aesinvsboxword invsbox0(ShiftRowOut[31:0], SboxOut[31:0]); aesinvsboxword invsbox1(ShiftRowOut[63:32], SboxOut[63:32]); - mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn); + mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn); // Apply inverse mixword to sbox outputs aesinvmixcolumns invmw0(MixcolIn[31:0], MixcolOut[31:0]); diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv deleted file mode 100644 index 2a96de7fc..000000000 --- a/src/ieu/aes_instructions/aes64im.sv +++ /dev/null @@ -1,35 +0,0 @@ -/////////////////////////////////////////// -// aes64im.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: aes64im instruction: RV64 accelerator mixcolumns and create decryption keyschedule -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module aes64im( - input logic [63:0] rs1, - output logic [63:0] result -); - - aesinvmixcolumns inv_mw_0(rs1[31:0], result[31:0]); - aesinvmixcolumns inv_mw_1(rs1[63:32], result[63:32]); -endmodule diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index b4b4c82a9..898304684 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -52,7 +52,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result - logic [P.XLEN-1:0] ZKNResult; // ZKNE or ZKND Result + logic [P.XLEN-1:0] ZKNDEResult; // ZKNE or ZKND Result logic [P.XLEN-1:0] MaskB; // BitMask of B logic [P.XLEN-1:0] RevA; // Bit-reversed A logic Mask; // Indicates if it is ZBS instruction @@ -120,14 +120,14 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( if (P.ZKNE_SUPPORTED) aes32e aes32e(.bs(Funct7[6:5]), .rs1(ABMU), .rs2(BBMU), .finalround(ZBBSelect[2]), .result(ZKNEResult)); // Select result if both decrypt and encrypt are supported if (P.ZKND_SUPPORTED & P.ZKNE_SUPPORTED) - mux2 #(32) zknmux(ZKNDResult, ZKNEResult, ZBBSelect[0], ZKNResult); + mux2 #(32) zknmux(ZKNDResult, ZKNEResult, ZBBSelect[0], ZKNDEResult); else if (P.ZKND_SUPPORTED) - assign ZKNResult = ZKNDResult; + assign ZKNDEResult = ZKNDResult; else - assign ZKNResult = ZKNEResult; + assign ZKNDEResult = ZKNEResult; end else if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin - zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNResult); + zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); end // ZKNH Unit @@ -147,8 +147,8 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( 4'b0011: ALUResult = ZBCResult; 4'b0100: ALUResult = ZBKBResult; 4'b0110: ALUResult = ZBKXResult; - 4'b0111: ALUResult = ZKNResult; - 4'b1000: ALUResult = ZKNResult; + 4'b0111: ALUResult = ZKNDEResult; + 4'b1000: ALUResult = ZKNDEResult; 4'b1001: ALUResult = ZKNHResult; default: ALUResult = PreALUResult; endcase diff --git a/src/ieu/kmu/zknde64.sv b/src/ieu/kmu/zknde64.sv index 290ae2264..cae271f89 100644 --- a/src/ieu/kmu/zknde64.sv +++ b/src/ieu/kmu/zknde64.sv @@ -31,7 +31,7 @@ module zknde64 import cvw::*; #(parameter cvw_t P) ( input logic [6:0] Funct7, input logic [3:0] round, input logic [3:0] ZKNSelect, - output logic [63:0] ZKNResult + output logic [63:0] ZKNDEResult ); logic [63:0] aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res; @@ -46,5 +46,5 @@ module zknde64 import cvw::*; #(parameter cvw_t P) ( aes64ks2 aes64ks2(.rs2(B), .rs1(A), .result(aes64ks2Res)); // Choose among decrypt, encrypt, key schedule 1, key schedule 2 results - mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNResult); + mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNDEResult); endmodule