From 39bf6a456e65503c0b7bca0ef77cebd169929a13 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Thu, 3 Nov 2022 22:37:25 +0000
Subject: [PATCH] renamed remOp to RemOp

---
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv         | 2 +-
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index b992a0d83..604a0711f 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -81,6 +81,6 @@ module fdivsqrt(
     .DivBusy);
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
-    .SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
+    .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
     .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 4600dfbd2..92bb1bd9b 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -38,7 +38,7 @@ module fdivsqrtpostproc(
   input  logic  Firstun,
   input  logic SqrtM,
   input  logic SpecialCaseM,
-  input  logic remOp,
+  input  logic RemOp,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM