From 397783812d0b5f9b4aaedb9147ebfed309f7c1e8 Mon Sep 17 00:00:00 2001 From: Daniel Torres Date: Fri, 17 Jun 2022 21:15:42 -0700 Subject: [PATCH] embench and testbench now support running both O2 and Os build variations without overwriting one another --- benchmarks/embench/Makefile | 47 +++++++++++++-------- pipelined/testbench/testbench.sv | 3 +- pipelined/testbench/tests.vh | 70 +++++++++++++++++++++----------- 3 files changed, 76 insertions(+), 44 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 3d1680585..255ea8be5 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -4,20 +4,29 @@ embench_dir = ../../addins/embench-iot -all: sim size +all: build sim size allClean: clean all build: buildspeed buildsize +buildspeed: build_speedopt_speed build_sizeopt_speed +buildsize: build_speedopt_size build_sizeopt_size -# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed -buildspeed: - $(embench_dir)/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" - find $(embench_dir)/bd_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size +build_speedopt_speed: + $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done -# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for size -buildsize: - $(embench_dir)/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0" +build_sizeopt_speed: + $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done + +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size +build_speedopt_size: + $(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-O2 -msave-restore" --dummy-libs="libgcc libm libc crt0" + +build_sizeopt_size: + $(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0" # builds dependencies, then launches modelsim and finally runs python wrapper script to present results sim: modelsim_build_memfile modelsim_run speed @@ -28,35 +37,37 @@ modelsim_run: cd ../../benchmarks/embench/ # builds the objdump based on the compiled c elf files -objdump: buildspeed - find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done +objdump: + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done # build memfiles, objdump.lab and objdump.addr files modelsim_build_memfile: objdump - find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done - find $(embench_dir)/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done # builds the tests for speed, runs them on spike and then launches python script to present results # note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim # you'll need to manually remove one of the two .output files, or run make clean -spike: buildspeed objdump spike_run speed +spike: buildspeed spike_run speed # command to run spike on all of the benchmarks spike_run: - find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done + find $(embench_dir)/bd_*opt_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done # python wrapper to present results of embench size benchmark size: buildsize - $(embench_dir)/benchmark_size.py --builddir=bd_size --json-output > wallySize.json + $(embench_dir)/benchmark_size.py --builddir=bd_speedopt_size --json-output > wallySpeedOpt_size.json + $(embench_dir)/benchmark_size.py --builddir=bd_sizeopt_size --json-output > wallySizeOpt_size.json # python wrapper to present results of embench speed benchmark speed: - $(embench_dir)/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySpeed.json + $(embench_dir)/benchmark_speed.py --builddir=bd_sizeopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySizeOpt_speed.json + $(embench_dir)/benchmark_speed.py --builddir=bd_speedopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySpeedOpt_speed.json # deletes all files clean: - rm -rf $(embench_dir)/bd_speed/ - rm -rf $(embench_dir)/bd_size/ + rm -rf $(embench_dir)/bd_*_speed/ + rm -rf $(embench_dir)/bd_*_size/ allclean: clean rm -rf $(embench_dir)/logs/ diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e442d27ad..712b0391e 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -65,7 +65,7 @@ logic [3:0] dummy; logic [`XLEN-1:0] PCW; string ProgramAddrMapFile, ProgramLabelMapFile; - integer ProgramAddrLabelArray [string]; + integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; logic DCacheFlushDone, DCacheFlushStart; @@ -197,7 +197,6 @@ logic [3:0] dummy; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) - ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 }; updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); reset_ext = 1; # 42; reset_ext = 0; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 72128e097..a492fdb21 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -37,8 +37,8 @@ string tvpaths[] = '{ "../../tests/wally-riscv-arch-test/work/", "../../tests/imperas-riscv-tests/work/", "../../benchmarks/riscv-coremark/work/", - "../../addins/embench-iot/bd_speed/src/" -}; + "../../addins/embench-iot/" + }; string coremark[] = '{ `COREMARK, @@ -47,28 +47,50 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, - "aha-mont64/aha-mont64", - "crc32/crc32", - "cubic/cubic", - "edn/edn", - "huffbench/huffbench", - "matmult-int/matmult-int", - "md5sum/md5sum", - "minver/minver", - "nbody/nbody", - "nettle-aes/nettle-aes", - "nettle-sha256/nettle-sha256", - "nsichneu/nsichneu", - "picojpeg/picojpeg", - "primecount/primecount", - "qrduino/qrduino", - "sglib-combined/sglib-combined", - "slre/slre", - "st/st", - "statemate/statemate", - "tarfind/tarfind", - "ud/ud", - "wikisort/wikisort" + "bd_speedopt_speed/src/aha-mont64/aha-mont64", + "bd_speedopt_speed/src/crc32/crc32", + "bd_speedopt_speed/src/cubic/cubic", + "bd_speedopt_speed/src/edn/edn", + "bd_speedopt_speed/src/huffbench/huffbench", + "bd_speedopt_speed/src/matmult-int/matmult-int", + "bd_speedopt_speed/src/md5sum/md5sum", + "bd_speedopt_speed/src/minver/minver", + "bd_speedopt_speed/src/nbody/nbody", + "bd_speedopt_speed/src/nettle-aes/nettle-aes", + "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", + "bd_speedopt_speed/src/nsichneu/nsichneu", + "bd_speedopt_speed/src/picojpeg/picojpeg", + "bd_speedopt_speed/src/primecount/primecount", + "bd_speedopt_speed/src/qrduino/qrduino", + "bd_speedopt_speed/src/sglib-combined/sglib-combined", + "bd_speedopt_speed/src/slre/slre", + "bd_speedopt_speed/src/st/st", + "bd_speedopt_speed/src/statemate/statemate", + "bd_speedopt_speed/src/tarfind/tarfind", + "bd_speedopt_speed/src/ud/ud", + "bd_speedopt_speed/src/wikisort/wikisort", + "bd_sizeopt_speed/src/aha-mont64/aha-mont64", + "bd_sizeopt_speed/src/crc32/crc32", + "bd_sizeopt_speed/src/cubic/cubic", + "bd_sizeopt_speed/src/edn/edn", + "bd_sizeopt_speed/src/huffbench/huffbench", + "bd_sizeopt_speed/src/matmult-int/matmult-int", + "bd_sizeopt_speed/src/md5sum/md5sum", + "bd_sizeopt_speed/src/minver/minver", + "bd_sizeopt_speed/src/nbody/nbody", + "bd_sizeopt_speed/src/nettle-aes/nettle-aes", + "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", + "bd_sizeopt_speed/src/nsichneu/nsichneu", + "bd_sizeopt_speed/src/picojpeg/picojpeg", + "bd_sizeopt_speed/src/primecount/primecount", + "bd_sizeopt_speed/src/qrduino/qrduino", + "bd_sizeopt_speed/src/sglib-combined/sglib-combined", + "bd_sizeopt_speed/src/slre/slre", + "bd_sizeopt_speed/src/st/st", + "bd_sizeopt_speed/src/statemate/statemate", + "bd_sizeopt_speed/src/tarfind/tarfind", + "bd_sizeopt_speed/src/ud/ud", + "bd_sizeopt_speed/src/wikisort/wikisort" }; string wally64a[] = '{