From 396cea1ea77096f8021fce808901db41864fed8d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 30 Jan 2021 11:50:37 -0500
Subject: [PATCH] Reorganized src hierarchically

---
 wally-pipelined/lint-wally                        |  2 +-
 .../regression/wally-pipelined-batch.do           |  3 +--
 wally-pipelined/regression/wally-pipelined.do     | 15 +++++++++++++--
 wally-pipelined/src/{ => dcu}/dcu.sv              |  0
 wally-pipelined/src/{ => ebu}/ahblite.sv          |  0
 wally-pipelined/src/{ => ebu}/subwordread.sv      |  0
 wally-pipelined/src/{ => generic}/flop.sv         |  0
 wally-pipelined/src/{ => generic}/mux.sv          |  0
 wally-pipelined/src/{ => hazard}/hazard.sv        |  0
 wally-pipelined/src/{ => ieu}/alu.sv              |  0
 wally-pipelined/src/{ => ieu}/controller.sv       |  0
 wally-pipelined/src/{ => ieu}/datapath.sv         |  0
 wally-pipelined/src/{ => ieu}/extend.sv           |  0
 wally-pipelined/src/{ => ieu}/ieu.sv              |  0
 wally-pipelined/src/{ => ieu}/regfile.sv          |  0
 wally-pipelined/src/{ => ieu}/shifter.sv          |  0
 wally-pipelined/src/{ => ifu}/decompress.sv       |  0
 wally-pipelined/src/{ => ifu}/ifu.sv              |  0
 wally-pipelined/src/{ => privileged}/csr.sv       |  0
 wally-pipelined/src/{ => privileged}/csrc.sv      |  0
 wally-pipelined/src/{ => privileged}/csri.sv      |  0
 wally-pipelined/src/{ => privileged}/csrm.sv      |  0
 wally-pipelined/src/{ => privileged}/csrn.sv      |  0
 wally-pipelined/src/{ => privileged}/csrs.sv      |  0
 wally-pipelined/src/{ => privileged}/csrsr.sv     |  0
 wally-pipelined/src/{ => privileged}/csru.sv      |  0
 wally-pipelined/src/{ => privileged}/privdec.sv   |  0
 .../src/{ => privileged}/privileged.sv            |  0
 wally-pipelined/src/{ => privileged}/trap.sv      |  0
 wally-pipelined/src/{ => uncore}/adrdec.sv        |  0
 wally-pipelined/src/{ => uncore}/clint.sv         |  0
 wally-pipelined/src/{ => uncore}/dtim.sv          |  1 +
 wally-pipelined/src/{ => uncore}/gpio.sv          |  0
 wally-pipelined/src/{ => uncore}/imem.sv          |  0
 wally-pipelined/src/{ => uncore}/subwordwrite.sv  |  0
 wally-pipelined/src/{ => uncore}/uart.sv          |  0
 wally-pipelined/src/{ => uncore}/uartPC16550D.sv  |  0
 wally-pipelined/src/{ => uncore}/uncore.sv        |  0
 .../src/{ => wally}/wallypipelinedhart.sv         |  3 +--
 .../src/{ => wally}/wallypipelinedsoc.sv          |  0
 wally-pipelined/testbench/testbench-imperas.sv    |  1 +
 41 files changed, 18 insertions(+), 7 deletions(-)
 rename wally-pipelined/src/{ => dcu}/dcu.sv (100%)
 rename wally-pipelined/src/{ => ebu}/ahblite.sv (100%)
 rename wally-pipelined/src/{ => ebu}/subwordread.sv (100%)
 rename wally-pipelined/src/{ => generic}/flop.sv (100%)
 rename wally-pipelined/src/{ => generic}/mux.sv (100%)
 rename wally-pipelined/src/{ => hazard}/hazard.sv (100%)
 rename wally-pipelined/src/{ => ieu}/alu.sv (100%)
 rename wally-pipelined/src/{ => ieu}/controller.sv (100%)
 rename wally-pipelined/src/{ => ieu}/datapath.sv (100%)
 rename wally-pipelined/src/{ => ieu}/extend.sv (100%)
 rename wally-pipelined/src/{ => ieu}/ieu.sv (100%)
 rename wally-pipelined/src/{ => ieu}/regfile.sv (100%)
 rename wally-pipelined/src/{ => ieu}/shifter.sv (100%)
 rename wally-pipelined/src/{ => ifu}/decompress.sv (100%)
 rename wally-pipelined/src/{ => ifu}/ifu.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csr.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csrc.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csri.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csrm.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csrn.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csrs.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csrsr.sv (100%)
 rename wally-pipelined/src/{ => privileged}/csru.sv (100%)
 rename wally-pipelined/src/{ => privileged}/privdec.sv (100%)
 rename wally-pipelined/src/{ => privileged}/privileged.sv (100%)
 rename wally-pipelined/src/{ => privileged}/trap.sv (100%)
 rename wally-pipelined/src/{ => uncore}/adrdec.sv (100%)
 rename wally-pipelined/src/{ => uncore}/clint.sv (100%)
 rename wally-pipelined/src/{ => uncore}/dtim.sv (97%)
 rename wally-pipelined/src/{ => uncore}/gpio.sv (100%)
 rename wally-pipelined/src/{ => uncore}/imem.sv (100%)
 rename wally-pipelined/src/{ => uncore}/subwordwrite.sv (100%)
 rename wally-pipelined/src/{ => uncore}/uart.sv (100%)
 rename wally-pipelined/src/{ => uncore}/uartPC16550D.sv (100%)
 rename wally-pipelined/src/{ => uncore}/uncore.sv (100%)
 rename wally-pipelined/src/{ => wally}/wallypipelinedhart.sv (97%)
 rename wally-pipelined/src/{ => wally}/wallypipelinedsoc.sv (100%)

diff --git a/wally-pipelined/lint-wally b/wally-pipelined/lint-wally
index 39b0f2a2d..198e8969b 100755
--- a/wally-pipelined/lint-wally
+++ b/wally-pipelined/lint-wally
@@ -1,7 +1,7 @@
 # check for warnings in Verilog code
 # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
 
-verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*.sv
+verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv
 
 # --lint-only just runs lint rather than trying to compile and simulate
 # -I points to the include directory where files such as `include wally-config.vh  are found
diff --git a/wally-pipelined/regression/wally-pipelined-batch.do b/wally-pipelined/regression/wally-pipelined-batch.do
index 1bcd1475a..883721d26 100644
--- a/wally-pipelined/regression/wally-pipelined-batch.do
+++ b/wally-pipelined/regression/wally-pipelined-batch.do
@@ -27,8 +27,7 @@ vlib work
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-#vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
-vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
+vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do
index c3d9ed19d..b7f41535d 100644
--- a/wally-pipelined/regression/wally-pipelined.do
+++ b/wally-pipelined/regression/wally-pipelined.do
@@ -30,8 +30,8 @@ vlib work
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined.do ../config/rv32ic
 switch $argc {
-    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583}
-    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583}
+    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
 }
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
@@ -44,6 +44,17 @@ view wave
 # Diplays All Signals recursively
 add wave /testbench/clk
 add wave /testbench/reset
+add wave -divider
+add wave /testbench/dut/hart/ebu/IReadF
+add wave /testbench/dut/hart/DataStall
+add wave /testbench/dut/hart/InstrStall
+add wave /testbench/dut/hart/StallF
+add wave /testbench/dut/hart/StallD
+add wave /testbench/dut/hart/FlushD
+add wave /testbench/dut/hart/FlushE
+add wave /testbench/dut/hart/FlushM
+add wave /testbench/dut/hart/FlushW
+
 add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCF
 add wave -hex /testbench/dut/hart/ifu/InstrF
diff --git a/wally-pipelined/src/dcu.sv b/wally-pipelined/src/dcu/dcu.sv
similarity index 100%
rename from wally-pipelined/src/dcu.sv
rename to wally-pipelined/src/dcu/dcu.sv
diff --git a/wally-pipelined/src/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
similarity index 100%
rename from wally-pipelined/src/ahblite.sv
rename to wally-pipelined/src/ebu/ahblite.sv
diff --git a/wally-pipelined/src/subwordread.sv b/wally-pipelined/src/ebu/subwordread.sv
similarity index 100%
rename from wally-pipelined/src/subwordread.sv
rename to wally-pipelined/src/ebu/subwordread.sv
diff --git a/wally-pipelined/src/flop.sv b/wally-pipelined/src/generic/flop.sv
similarity index 100%
rename from wally-pipelined/src/flop.sv
rename to wally-pipelined/src/generic/flop.sv
diff --git a/wally-pipelined/src/mux.sv b/wally-pipelined/src/generic/mux.sv
similarity index 100%
rename from wally-pipelined/src/mux.sv
rename to wally-pipelined/src/generic/mux.sv
diff --git a/wally-pipelined/src/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
similarity index 100%
rename from wally-pipelined/src/hazard.sv
rename to wally-pipelined/src/hazard/hazard.sv
diff --git a/wally-pipelined/src/alu.sv b/wally-pipelined/src/ieu/alu.sv
similarity index 100%
rename from wally-pipelined/src/alu.sv
rename to wally-pipelined/src/ieu/alu.sv
diff --git a/wally-pipelined/src/controller.sv b/wally-pipelined/src/ieu/controller.sv
similarity index 100%
rename from wally-pipelined/src/controller.sv
rename to wally-pipelined/src/ieu/controller.sv
diff --git a/wally-pipelined/src/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
similarity index 100%
rename from wally-pipelined/src/datapath.sv
rename to wally-pipelined/src/ieu/datapath.sv
diff --git a/wally-pipelined/src/extend.sv b/wally-pipelined/src/ieu/extend.sv
similarity index 100%
rename from wally-pipelined/src/extend.sv
rename to wally-pipelined/src/ieu/extend.sv
diff --git a/wally-pipelined/src/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
similarity index 100%
rename from wally-pipelined/src/ieu.sv
rename to wally-pipelined/src/ieu/ieu.sv
diff --git a/wally-pipelined/src/regfile.sv b/wally-pipelined/src/ieu/regfile.sv
similarity index 100%
rename from wally-pipelined/src/regfile.sv
rename to wally-pipelined/src/ieu/regfile.sv
diff --git a/wally-pipelined/src/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
similarity index 100%
rename from wally-pipelined/src/shifter.sv
rename to wally-pipelined/src/ieu/shifter.sv
diff --git a/wally-pipelined/src/decompress.sv b/wally-pipelined/src/ifu/decompress.sv
similarity index 100%
rename from wally-pipelined/src/decompress.sv
rename to wally-pipelined/src/ifu/decompress.sv
diff --git a/wally-pipelined/src/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
similarity index 100%
rename from wally-pipelined/src/ifu.sv
rename to wally-pipelined/src/ifu/ifu.sv
diff --git a/wally-pipelined/src/csr.sv b/wally-pipelined/src/privileged/csr.sv
similarity index 100%
rename from wally-pipelined/src/csr.sv
rename to wally-pipelined/src/privileged/csr.sv
diff --git a/wally-pipelined/src/csrc.sv b/wally-pipelined/src/privileged/csrc.sv
similarity index 100%
rename from wally-pipelined/src/csrc.sv
rename to wally-pipelined/src/privileged/csrc.sv
diff --git a/wally-pipelined/src/csri.sv b/wally-pipelined/src/privileged/csri.sv
similarity index 100%
rename from wally-pipelined/src/csri.sv
rename to wally-pipelined/src/privileged/csri.sv
diff --git a/wally-pipelined/src/csrm.sv b/wally-pipelined/src/privileged/csrm.sv
similarity index 100%
rename from wally-pipelined/src/csrm.sv
rename to wally-pipelined/src/privileged/csrm.sv
diff --git a/wally-pipelined/src/csrn.sv b/wally-pipelined/src/privileged/csrn.sv
similarity index 100%
rename from wally-pipelined/src/csrn.sv
rename to wally-pipelined/src/privileged/csrn.sv
diff --git a/wally-pipelined/src/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
similarity index 100%
rename from wally-pipelined/src/csrs.sv
rename to wally-pipelined/src/privileged/csrs.sv
diff --git a/wally-pipelined/src/csrsr.sv b/wally-pipelined/src/privileged/csrsr.sv
similarity index 100%
rename from wally-pipelined/src/csrsr.sv
rename to wally-pipelined/src/privileged/csrsr.sv
diff --git a/wally-pipelined/src/csru.sv b/wally-pipelined/src/privileged/csru.sv
similarity index 100%
rename from wally-pipelined/src/csru.sv
rename to wally-pipelined/src/privileged/csru.sv
diff --git a/wally-pipelined/src/privdec.sv b/wally-pipelined/src/privileged/privdec.sv
similarity index 100%
rename from wally-pipelined/src/privdec.sv
rename to wally-pipelined/src/privileged/privdec.sv
diff --git a/wally-pipelined/src/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
similarity index 100%
rename from wally-pipelined/src/privileged.sv
rename to wally-pipelined/src/privileged/privileged.sv
diff --git a/wally-pipelined/src/trap.sv b/wally-pipelined/src/privileged/trap.sv
similarity index 100%
rename from wally-pipelined/src/trap.sv
rename to wally-pipelined/src/privileged/trap.sv
diff --git a/wally-pipelined/src/adrdec.sv b/wally-pipelined/src/uncore/adrdec.sv
similarity index 100%
rename from wally-pipelined/src/adrdec.sv
rename to wally-pipelined/src/uncore/adrdec.sv
diff --git a/wally-pipelined/src/clint.sv b/wally-pipelined/src/uncore/clint.sv
similarity index 100%
rename from wally-pipelined/src/clint.sv
rename to wally-pipelined/src/uncore/clint.sv
diff --git a/wally-pipelined/src/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
similarity index 97%
rename from wally-pipelined/src/dtim.sv
rename to wally-pipelined/src/uncore/dtim.sv
index a3f69ee47..486f902fd 100644
--- a/wally-pipelined/src/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -77,6 +77,7 @@ module dtim (
       assign #2 entry = HADDR[17:2]; 
   endgenerate
   assign HREADTim = RAM[entry];
+//  assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready
 
   // write each byte based on the byte mask
   // UInstantiate a byte-writable memory here if possible
diff --git a/wally-pipelined/src/gpio.sv b/wally-pipelined/src/uncore/gpio.sv
similarity index 100%
rename from wally-pipelined/src/gpio.sv
rename to wally-pipelined/src/uncore/gpio.sv
diff --git a/wally-pipelined/src/imem.sv b/wally-pipelined/src/uncore/imem.sv
similarity index 100%
rename from wally-pipelined/src/imem.sv
rename to wally-pipelined/src/uncore/imem.sv
diff --git a/wally-pipelined/src/subwordwrite.sv b/wally-pipelined/src/uncore/subwordwrite.sv
similarity index 100%
rename from wally-pipelined/src/subwordwrite.sv
rename to wally-pipelined/src/uncore/subwordwrite.sv
diff --git a/wally-pipelined/src/uart.sv b/wally-pipelined/src/uncore/uart.sv
similarity index 100%
rename from wally-pipelined/src/uart.sv
rename to wally-pipelined/src/uncore/uart.sv
diff --git a/wally-pipelined/src/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
similarity index 100%
rename from wally-pipelined/src/uartPC16550D.sv
rename to wally-pipelined/src/uncore/uartPC16550D.sv
diff --git a/wally-pipelined/src/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
similarity index 100%
rename from wally-pipelined/src/uncore.sv
rename to wally-pipelined/src/uncore/uncore.sv
diff --git a/wally-pipelined/src/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
similarity index 97%
rename from wally-pipelined/src/wallypipelinedhart.sv
rename to wally-pipelined/src/wally/wallypipelinedhart.sv
index 2814f3437..685d2ac19 100644
--- a/wally-pipelined/src/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -96,13 +96,12 @@ module wallypipelinedhart (
   dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
 
   ahblite ebu( // *** make IRData InstrF
-    .IPAdrF(PCF), .IReadF(1'b0), .IRData(), //.IReady(), 
+    .IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(), 
     .DPAdrM(DataAdrM), .DReadM(MemRWdcuoutM[1]), .DWriteM(MemRWdcuoutM[0]), .DWDataM(WriteDataM), 
     .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), 
     .UnsignedLoadM(Funct3M[2]),
     .*);
   //assign InstrF = ReadDataM[31:0];
-//  assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
 
 /*  
   mdu mdu(.*); // multiply and divide unit
diff --git a/wally-pipelined/src/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
similarity index 100%
rename from wally-pipelined/src/wallypipelinedsoc.sv
rename to wally-pipelined/src/wally/wallypipelinedsoc.sv
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 3e818a8f3..67a896445 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -75,6 +75,7 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
+                     "rv64i/I-LW-01", "4110",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
                      "rv64i/I-ADDIW-01", "3000",