renamed debug to extended signature

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1.

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S

@@ -29,7 +29,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.5 Unvectored interrupt tests 
 
-TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
 csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1
+TRAP_HANDLER m, EXT_SIGNATURE=1
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S

@@ -27,8 +27,8 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
+TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode
-TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. 
+TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. 
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S

@@ -26,7 +26,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x200000
 csrs mstatus, x28 // set mstatus.TW bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.5 Unvectored interrupt tests 
 
-TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
+TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // necessary to handle changing modes
-TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.4 Basic trap tests 
 
-TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
+TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary to handle switching privilege modes
-TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
 
@@ -64,7 +64,7 @@ jal cause_m_ext_interrupt
 
 // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
 // We can tell which one becuase the different trap handler modes write different bits of the status register 
-// to the output when debug is on.
+// to the output when EXT_SIGNATURE is on.
 
 GOTO_M_MODE // so we can write the delegate registers
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1
+TRAP_HANDLER m, EXT_SIGNATURE=1
 
 // test 5.3.1.6 Interrupt enabling and priority tests 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.4 Basic trap tests 
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
-TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
 
@@ -61,7 +61,7 @@ jal cause_m_ext_interrupt
 
 // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
 // We can tell which one becuase the different trap handler modes write different bits of the status register 
-// to the output when debug is on.
+// to the output when EXT_SIGNATURE is on.
 
 GOTO_M_MODE // so we can write the delegate registers
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1.

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S

@@ -29,7 +29,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.5 Unvectored interrupt tests 
 
-TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
 csrs mstatus, x28 // set sstatus.MIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1
+TRAP_HANDLER m, EXT_SIGNATURE=1
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S

@@ -27,8 +27,8 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
+TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode
-TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. 
+TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. 
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S

@@ -26,7 +26,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x200000
 csrs mstatus, x28 // set mstatus.TW bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.5 Unvectored interrupt tests 
 
-TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
+TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // necessary to handle changing modes
-TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x2
 csrs sstatus, x28 // set sstatus.SIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S

@@ -27,7 +27,7 @@ INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.4 Basic trap tests 
 
-TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
+TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary to handle switching privilege modes
-TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
 
@@ -64,7 +64,7 @@ jal cause_m_ext_interrupt
 
 // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
 // We can tell which one becuase the different trap handler modes write different bits of the status register 
-// to the output when debug is on.
+// to the output when EXT_SIGNATURE is on.
 
 GOTO_M_MODE // so we can write the delegate registers
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1
+TRAP_HANDLER m, EXT_SIGNATURE=1
 
 // test 5.3.1.6 Interrupt enabling and priority tests 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S

@@ -29,8 +29,8 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 
 // test 5.3.1.4 Basic trap tests 
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
-TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
 
 // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
 
@@ -61,7 +61,7 @@ jal cause_m_ext_interrupt
 
 // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
 // We can tell which one becuase the different trap handler modes write different bits of the status register 
-// to the output when debug is on.
+// to the output when EXT_SIGNATURE is on.
 
 GOTO_M_MODE // so we can write the delegate registers
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1